DETAILED ACTION
This office action is in response to the election filed 1/5/2026.
Currently, claims 1-20 are pending.
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 19-20 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: In para. [0006] and [0033], “Al2O2” is used as the formula for aluminum oxide. However, Al2O2 is not known to be a stable compound. “Al2O2” appears to be erroneous. Presumably, Al2O3 is the aluminum oxide compound.
Appropriate correction is required.
Claim Objections
Claims 1, 6 and 19 are objected to because of the following informalities:
Pertaining to claim 1, a word such as “the” or “said” is missing preceding “interlayer insulating layer” in line 14.
Pertaining to claims 6 and 19, as noted above, “Al2O-2” is believed to be erroneous and should instead be “Al2O3”.
Furthermore, as it pertains to claim 19, the limitation “wherein the interlayer insulating layer includes silicon oxide” is recited in lines 4-5 and then repeated in line 17.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “based on top surfaces of the first conductive layer and the dielectric layer, a vertical length of the dielectric layer is less than or equal to a vertical length of the first conductive layer”. It is not clear how the top surfaces, which are two-dimensional in the x-y plane, determine a basis for vertical length, which is presumably a single dimension along the z-direction. The claim will be examined as best understood by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 11,004,740).
Pertaining to claim 1, Yang shows, with reference to FIG. 2Q and 2P, an integrated circuit device comprising an interconnection structure, wherein the interconnection structure comprises:
an interlayer insulating layer (222) arranged on a substrate (202) and having a plurality of trenches (230/232) formed in the interlayer insulating layer;
a first conductive layer (234) formed inside a first trench (left trench) of the plurality of trenches;
a second conductive layer (234) formed inside a second trench (center trench) of the plurality of trenches, wherein the second trench is spaced apart from the first trench of the plurality of trenches in a first direction;
a third conductive layer (234) formed inside a third trench (right trench) of the plurality of trenches, wherein the third trench is spaced apart from the second trench of the plurality of trenches in the first direction; and
a dielectric layer (portion 221 of 218, see FIG. 2L) formed between the first conductive layer and the second conductive layer,
wherein a portion of the interlayer insulating layer (222) is disposed between the second conductive layer and the third conductive layer (FIG. 2Q), and
wherein a first width of the first conductive layer in the first direction (e.g. width of portion in 232) is greater than a second width of the second conductive layer in the first direction (e.g. width of portion in 230).
Pertaining to claim 2, Yang shows the dielectric layer comprises a material having an etch selectivity with respect to the interlayer insulating layer (col. 5, lines 54-56).
Pertaining to claim 3, Yang shows a first distance between a center of the first conductive layer in the first direction and a center of the second conductive layer in the first direction is greater than or equal to a second distance between a center of the second conductive layer in the first direction and a center of the third conductive layer in the first direction (FIG. 2Q).
Pertaining to claim 4, the vertical length of 234 is shown to be greater than the vertical length of 221.
Pertaining to claim 5, Yang shows the interlayer insulating layer may comprise silicon oxide (col. 6, lines 50-52; col. 8, lines 50-51).
Pertaining to claim 6, Yang shows the dielectric layer comprises silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), aluminum oxide (AlO3), aluminum nitride (AlN), titanium oxide (TiO2), or a combination thereof (col. 5, lines 58-60).
Pertaining to claim 9, Yang shows a first separation distance between the first conductive layer and the second conductive layer in the first direction is less than or equal to a second separation distance between the second conductive layer and the third conductive layer in the first direction (FIG. 2Q).
Pertaining to claim 19, Yang shows an integrated circuit device comprising an interconnection structure, wherein the interconnection structure comprises:
an interlayer insulating layer (222) arranged on a substrate and having a plurality of trenches (230/232) formed in the interlayer insulating layer, wherein the interlayer insulating layer includes silicon oxide (col. 6, lines 50-52; col. 8, lines 50-51);
a first conductive layer (234) formed inside a first trench (left trench) of the plurality of trenches;
a second conductive layer (234) formed inside a second trench (center trench) of the plurality of trenches, wherein the second trench is spaced apart from the first trench of the plurality of trenches in a first direction;
a third conductive layer (234) formed inside a third trench (right trench) of the plurality of trenches, wherein the third trench is spaced apart from the second trench of the plurality of trenches in the first direction; and
a dielectric layer (portion 221 of 218, see FIG. 2L) formed between the first conductive layer and the second conductive layer and including silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), aluminum oxide (AlO3), aluminum nitride (AlN), titanium oxide (TiO2), or a combination thereof (col. 5, lines 58-60), which have an etch selectivity with respect to the interlayer insulating layer (col. 5, lines 54-56),
wherein the interlayer insulating layer includes silicon oxide (col. 6, lines 50-52; col. 8, lines 50-51), and a portion of the interlayer insulating layer (222) is disposed between the second conductive layer and the third conductive layer (FIG. 2Q), and
wherein a first width of the first conductive layer in the first direction (e.g. width of portion in 232) is greater than a second width of the second conductive layer in the first direction (e.g. width of portion in 230), and
a first separation distance between the first conductive layer and the second conductive layer in the first direction is less than or equal to a second separation distance between the second conductive layer and the third conductive layer in the first direction (FIG. 2Q).
In an alternative interpretation, considering the interlayer insulating layer is a dielectric material, layer 222 may be interpreted both as an interlayer insulating layer and a dielectric layer. In this case, as it pertains to claim 1, Yang shows an integrated circuit device comprising an interconnection structure, wherein the interconnection structure comprises:
an interlayer insulating layer (222) arranged on a substrate (202) and having a plurality of trenches (230/232) formed in the interlayer insulating layer;
a first conductive layer (234) formed inside a first trench (left trench) of the plurality of trenches;
a second conductive layer (234) formed inside a second trench (center trench) of the plurality of trenches, wherein the second trench is spaced apart from the first trench of the plurality of trenches in a first direction;
a third conductive layer (234) formed inside a third trench (right trench) of the plurality of trenches, wherein the third trench is spaced apart from the second trench of the plurality of trenches in the first direction; and
a dielectric layer (222) formed between the first conductive layer and the second conductive layer,
wherein a portion of the interlayer insulating layer (222) is disposed between the second conductive layer and the third conductive layer (FIG. 2Q), and
wherein a first width of the first conductive layer in the first direction (e.g. width of portion in 232) is greater than a second width of the second conductive layer in the first direction (e.g. width of portion in 230).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Referencing the alternative interpretation above, pertaining to claim 7, Yang shows the invention in cross-sectional view and therefore does not explicitly show a fourth conductive layer formed inside a fourth trench of the plurality of trenches, wherein the fourth trench is spaced apart from the second trench of the plurality of trenches in a second direction substantially perpendicular to the first direction, wherein the dielectric layer is formed between the second conductive layer and the fourth conductive layer.
However, the Examiner takes official notice that it is well known in the art that interconnection structures in an ILD such as those of Yang are not arranged in only one dimension, but rather interconnects are arranged in a two-dimensional array to service the devices formed in the wafer below. Thus, it would be obvious for interconnection structures to be arranged in front of and behind the interconnection structures depicted in the figures of Yang.
Pertaining to claim 8, although Yang does not explicitly show the claimed seed layer, the Examiner takes official notice that it is well established in the art to line the opening of an interconnect with a seed layer and use it to deposit the metal fill in the remainder of the opening. Thus, this would be obvious to one of ordinary skill in the art. Referencing FIG. 2Q, in the case that the openings are lined with a seed layer, the seed layer would be partially covered by the dielectric layer.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Although claim 20 recites the same limitations as claim 7, it depends on claim 19 which further recites “wherein the interlayer insulating layer includes silicon oxide” and “a dielectric layer … including silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), aluminum oxide (AlO3), aluminum nitride (AlN), titanium oxide (TiO2). Considering the difference in materials, the interpretation of Yang in which layer 222 is interpreted to be both the dielectric layer and the interlayer insulating layer cannot be applied to claim 20. Turning to the first interpretation, the dielectric layer is formed at a point in the fabrication process (Fig. 2J-L) that would result in deposition along sidewalls of a metal line extending in the second direction, and thus would not be located between conductive layers that are spaced apart in the second direction, as required by claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sakuma et al. (US 7,994,642) discloses an invention with a dielectric layer embedded in an interlayer dielectric layer between metal structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896