DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an
application filed in Japan on 03/09/2021. It is noted, however, that applicant has not filed a certified copy of the PCT/JP2021/009097 application as required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election with traverse of Species A in the reply filed on 11/07/2025
is acknowledged. Claims 9 – 26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/07/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a ground portion in contact with the movable portions of the plurality of ground connection terminals and electrically connected to the plurality of ground connection terminals." It is unclear if this should be interpreted as “ground portion of the transmission line body" or “ground portion of the interposer substrate”. For the purpose of the instant examination, the examiner interprets this limitation as “interposer substrate ground portion”.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "signal transmission line body" in lines 7 and 8. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Tarui et al. (US20180351595A1; hereinafter Tarui) in view of Shen (US20170287872A1; hereinafter Shen).
Regarding Claim 1, Tarui discloses a semiconductor module comprising:
a semiconductor element (RF device 122) having, on a front face thereof (fourth end face 202), a signal terminal (122a) and a ground terminal (210), FIG. 4, [0036], [0075], [0076];
a transmission line body (distribution circuit board 50) having a signal transmission portion (51C-1) and a ground portion (51C-2), FIGS. 9, 17 reproduced below, [0169];
a signal connection terminal (spring contact terminal 55 contacting RF signal pads 51A-1 and 51C-1) having a movable portion at a first end (portion of 55 contacting 51A-1 at face 102) thereof and a fixed portion located at a second end (portion of 55 contacting 51C-1 on the board 50) thereof and electrically connected to the signal transmission portion (51C-1) of the transmission line body (50), FIG. 17, [0169], [0172], [0173].
a plurality of ground connection terminals (plurality of spring contact terminal 55 contacting the ground pads 51A-2 and 51C-2) arranged to surround the signal connection terminal (spring contact terminal 55 contacting RF signal pads 51A-1 and 51C-1), each of the ground connection terminals (spring contact terminal 55 contacting the ground pads 51A-2 and 51C-2) having a movable portion at a first end (portion of 55 contacting 51A-2 at 102) thereof, and a fixed portion located at a second end thereof (portion of 55 contacting 51C-2 on the board 50) and electrically connected to the ground portion (51C-2) of the transmission line body (50), the plurality of ground connection terminals (plurality of spring contact terminal 55 contacting the ground pads 51A-2 and 51C-2) and the signal connection terminal (spring contact terminal 55 contacting RF signal pads 51A-1 and 51C-1) constituting a pseudo coaxial line, FIG. 17, [0165], [0169];
a heat dissipation plate having a front face (front face of cooling plate 300 with heat dissipation member 175) in close contact with a back face of the semiconductor element (inactive side of 122), FIG. 15, [0189];
a transmission-line-body signal pad (51A-1) in contact with the movable portion of the signal connection terminal (portion of 55 contacting 51A-1 at face 102) and electrically connected to the signal connection terminal (spring contact terminal 55 contacting RF signal pads 51A-1 and 51C-1), and a ground portion (51A-2) in contact with the movable portions of the plurality of ground connection terminals (portion of 55 contacting 51A-2 at 102) and electrically connected to the plurality of ground connection terminals (plurality of spring contact terminal 55 contacting the ground pads 51A-2 and 51C-2), FIG. 17, [0169], [0173].
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Tarui discloses semiconductor element 122 mounted on the multilayer substrate 100 and a cooling plate 300 arranged on a side of the second end face 102 of the multilayer resin substrate 100, but does not disclose “an interposer substrate having a front face disposed to face the front face of the heat dissipation plate, the interposer substrate having, on the front face, a semiconductor-element signal pad electrically connected to the signal terminal of the semiconductor element by a conductive adhesive.”
In a similar art, Shen discloses an integrated circuit package 100, FIG. 1, [0018].
Shen discloses: a heat dissipation plate (heat spreader 124) having a front face (surface facing the IC dies 102, 104) in close contact with a back face (inactive side) of the semiconductor element (102, 104), FIG. 1, [0022]; and
an interposer substrate (108) having a front face (facing the IC dies 102, 104) disposed to face the front face of the heat dissipation plate (124), the interposer substrate (108) having, on the front face (facing the IC dies 102, 104), a semiconductor-element signal pad (106) electrically connected to the signal terminal (105) of the semiconductor element (102, 104) by a conductive adhesive (bumpless attachment), FIG. 1, [0019], [0020]. Shen [0020] discloses a bumpless electrical connection by direct coupling of conductive pads 105 and 106 through a direct cold welding process or a covalence bond assist diffusion bonding process, but is not limited thereto, which indicates the electrical connection between conductive pads 105 and 106 can be formed using conductive adhesives.
Shen discloses that a package as taught improves heat dissipation and protects the semiconductor dies from external contaminants [0044]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui’s semiconductor module in order improve heat dissipation and protect the semiconductor dies as disclosed by Shen [0044].
Regarding Claim 2, The combination of Tarui and Shen disclose the semiconductor module according to claim 1.
Tarui discloses: wherein the semiconductor element (122) is a power amplifier (High Power Amplifier) mounted with a plurality of active elements (RF device 121 is a driver amplifier, the RF device 122 is an HPA, and the RF device 124 is a low noise amplifier) such as a high-frequency amplifier (122) and a transistor (a transistor chip 5), [0036], [0053], or a semiconductor integrated circuit device mounted with a plurality of passive components.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui in view of Shen, further in view of Ito et al. (JP6274358B1; hereinafter Ito).
Regarding Claim 3, The combination of Tarui and Shen disclose the semiconductor module according to claim 1.
The combination of Tarui and Shen does not disclose “wherein the heat dissipation plate has a protrusion that is a portion where the back face of the semiconductor element is in close contact.”
In a similar art, Ito discloses a semiconductor device constituting a package functioning as a power amplifier [0006].
Ito discloses: wherein the heat dissipation plate (10) has a protrusion (10a) that is a portion where the back face (inactive face) of the semiconductor element (7) is in close contact, FIGS. 3, 4, [0031].
Ito discloses that a semiconductor device as taught is capable of reducing cost and enhancing performance [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui and Shen’s semiconductor device in order to reduce cost and enhance performance as disclosed by Ito [0007].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui in view of Shen, further in view of Okabe et al. (JPH10125830A; hereinafter Okabe).
Regarding Claim 4, The combination of Tarui and Shen discloses the semiconductor module according to claim 1.
The combination of Tarui and Shen does not disclose “the transmission line body is a microstrip line having a dielectric substrate, the signal transmission portion of the transmission line body is a signal pad formed on a front face of the dielectric substrate and connected to a signal transmission line formed on the front face of the dielectric substrate, and the ground portion of the transmission line body is a ground conductor formed on the front face of the dielectric substrate and electrically separated from the signal transmission line body and the signal pad.”
In a similar art, Okabe discloses a high frequency module with a microstrip [0003].
Okabe discloses: wherein the transmission line body is a microstrip line having a dielectric substrate (wiring 202 having a micro strip line on a dielectric substrate 101), FIG. 3, [0003].
the signal transmission portion of the transmission line body is a signal pad (input and output terminal portion 203) formed on a front face of the dielectric substrate (main surface of 101) and connected to a signal transmission line (202) formed on the front face of the dielectric substrate (main surface of 101), FIG. 3, [0003], and
the ground portion of the transmission line body (ground portion 204) is a ground conductor (gold-plated ground conductor 204) formed on the front face of the dielectric substrate (main surface of 101) and electrically separated from the signal transmission line body and the signal pad (ground 204 is electrically separated from the wiring 202 and the terminal portion 203 by the insulating region between them), FIG. 3, [0003].
Okabe discloses that a package as taught improves heat dissipation and electromagnetic shielding [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui and Shen’s semiconductor module in order to improve heat dissipation and electromagnetic shielding as disclosed by Okabe [0003].
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tarui in view of Shen, further in view of Dohata (US20050206467A1; hereinafter Dohata).
Regarding Claim 5, The combination of Tarui and Shen disclose the semiconductor module according to claim 1.
Tarui discloses a distribution circuit board 50 (transmission line body) with RF signal pads 51C-1 and ground pads 51C-2, FIG. 17, [0169]. The combination of Tarui and Shen does not disclose “wherein the transmission line body is a microstrip line having a dielectric substrate, the signal transmission portion of the transmission line body is a signal pad formed on a back face of the dielectric substrate and connected to a signal transmission line formed on the back face of the dielectric substrate, and the ground portion of the transmission line body is a ground conductor formed on the front face of the dielectric substrate.”
In a similar art, Dohata discloses a microstrip line, FIG. 1, [0034].
Dohata discloses a microstrip line with a dielectric substrate 1, where a signal line 2c is on the other main surface of the dielectric substrate and ground patterns 3a, 3b, and 3c on the main surface of the dielectric substrate, FIG.1, [0034], [0035].
The combination of Tarui and Dohata disclose: wherein the transmission line body is a microstrip line having a dielectric substrate (Dohata: microstrip line including a dielectric substrate 1), the signal transmission portion of the transmission line body is a signal pad (Tarui: RF signal pads 51C-1) formed on a back face of the dielectric substrate (Dohata: dielectric substrate 1) and connected to a signal transmission line formed on the back face of the dielectric substrate (Dohata: signal line 2c provided on the back face of 1), and the ground portion of the transmission line body is a ground conductor formed on the front face of the dielectric substrate (Dohata: ground patterns 3a, 3b, 3c on the front face of 1), FIG. 1, [0034], [0035].
Dohata discloses that a module as taught suppresses electro-magnetic interference without increasing the dielectric substrate area [0010]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui and Shen’s semiconductor module in order to suppress electro-magnetic interference without increasing the dielectric substrate area as disclosed by Dohata [0010].
Regarding Claim 6, The combination of Tarui and Shen disclose the semiconductor module according to claim 1.
Tarui discloses a distribution circuit board 50 (transmission line body) with RF signal pads 51C-1 and ground pads 51C-2, FIG. 17, [0169]. The combination of Tarui and Shen does not disclose “wherein the transmission line body is a microstrip line having a dielectric substrate, the signal transmission portion of the transmission line body is a signal pad formed on the back face of the dielectric substrate and connected to a signal transmission line formed on the back face of the dielectric substrate, and the ground portion of the transmission line body is a ground conductor formed on the back face of the dielectric substrate.”
Dohata discloses a microstrip line with a dielectric substrate 1, where a signal line 2c and ground patterns 3d, 3e are on the other main surface of the dielectric substrate 1, FIG.1, [0035].
The combination of Tarui and Dohata disclose: wherein the transmission line body is a microstrip line having a dielectric substrate (Dohata: microstrip line including a dielectric substrate 1), the signal transmission portion of the transmission line body is a signal pad (Tarui: RF signal pads 51C-1) formed on a back face of the dielectric substrate (Dohata: dielectric substrate 1) and connected to a signal transmission line formed on the back face of the dielectric substrate (Dohata: signal line 2c provided on the back face of 1), and the ground portion of the transmission line body is a ground conductor formed on the back face of the dielectric substrate (Dohata: ground patterns 3d, 3e on the back face of 1), FIG. 1, [0035].
Dohata discloses that a module as taught suppresses electro-magnetic interference [0010]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui and Shen’s semiconductor module in order to suppress electro-magnetic interference as disclosed by Dohata [0010].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui in view of Shen, further in view of Dohata, still further in view of Walsh et al. (US20090085808A1; hereinafter Walsh).
Regarding Claim 7, The combination of Tarui, Shen, and Dohata disclose the semiconductor module according to claim 5.
The combination of Tarui, Shen, and Dohata does not disclose “wherein
the heat dissipation plate includes a recessed portion physically separated from the signal transmission portion and the signal transmission line of the transmission line body on the front face to which the signal transmission portion and the signal transmission line of the transmission line body face.”
In a similar art, Walsh discloses a microstrip line 54, FIG. 1, [0013].
Walsh discloses: wherein the heat dissipation plate (baseplate 12 for heat removal, [0004]) includes a recessed portion (cavity 16) physically separated from the signal transmission portion (probe 56) and the signal transmission line (microstrip line 54) of the transmission line body on the front face (first side 14) to which the signal transmission portion (probe 56) and the signal transmission line (54) of the transmission line body face, FIG. 1, [0010], [0013].
Walsh discloses that a package as taught improves heat dissipation [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui, Shen, and Dohata’s semiconductor device in order to improve heat dissipation as disclosed by Walsh [0004].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tarui in view of Shen, further in view of Dohata, still further in view of Degrenne (US20190043781A1; hereinafter Degrenne).
Regarding Claim 8, The combination of Tarui, Shen, and Dohata disclose the semiconductor module according to claim 5.
Tarui discloses a distribution circuit board 50 (transmission line body) with RF signal pads 51C-1 and ground pads 51C-2, FIG. 17, [0169]. Dohata discloses a microstrip line with a dielectric substrate 1, where a signal line 2c is on the other main surface of the dielectric substrate and ground patterns 3a, 3b, and 3c on the main surface of the dielectric substrate, FIG.1, [0034], [0035].
The combination of Tarui, Shen, and Dohata does not disclose “further comprising: a spacer between the back face of the transmission line body and the front face of the heat dissipation plate, the spacer surrounding the signal transmission portion and the signal transmission line of the transmission line body and physically separating the signal transmission portion and the signal transmission line of the transmission line body from the front face of the heat dissipation plate.”
In a similar art, Degrenne discloses a power module [0039].
Degrenne discloses a spacer (third material 115) disposed between the back of the substrate 110 and the top surface of the heat sink 125, and a cavity 32 is formed within the spacer, FIGS. 1, 3, [0049], [0051], [0056].
The combination of Tarui, Dohata and Degrenne disclose: further comprising: a spacer (Degrenne: 115 with cavity 32) between the back face of the transmission line body (Dohata: back face of dielectric substrate 1) and the front face of the heat dissipation plate (Degrenne: top of 125), the spacer (Degrenne: 115 with cavity 32) surrounding the signal transmission portion (Tarui: RF signal pads 51C-1) and the signal transmission line of the transmission line body (Dohata: signal line 2c on the dielectric substrate 1) and physically separating the signal transmission portion (Tarui: RF signal pads 51C-1) and the signal transmission line of the transmission line body (Dohata: signal line 2c on the dielectric substrate 1) from the front face of the heat dissipation plate (Degrenne: top of 125).
Degrenne discloses that a semiconductor device as taught improves cooling efficiency and electrical isolation thereby reducing cost [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tarui, Shen, and Dohata’s semiconductor device in order to reduce cost by improving cooling efficiency and electrical isolation as disclosed by Degrenne [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna Palaniswamy whose telephone number is
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for the organization where this application or proceeding is assigned is 571-273-8300.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899