DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicants’ 1 DEC 2025 election (REM page 10) without traverse of Invention I (semiconductor modules), Species I, shown in FIGS. 1, 7A-7D, and described in claims 1-15 is acknowledged. The 1 DEC 2025 cancellation of claims 16-20 has been entered. The 1 DEC 2025 addition of claims 21-23 has been entered.
In light of applicants’ preliminary amendment, the species restriction requirement is hereby withdrawn. Claims 1-15 and 21-23 are examined below. In view of the withdrawal of the species restriction requirement, applicant is advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Priority
Acknowledgment is made of applicants’ claim for foreign priority based on an application filed in KOREA on 12 AUG 2022. It is noted that applicants have filed a certified copy of said application as required by U.S.C 119, which papers have been placed of record in the file. See 24 SEP 2023 submission.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 APR 2024 was filed before the mailing of a first Office action on the merits. The submission follows provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Claim Objections
The following claim language lacks sufficient antecedent basis (MPEP § 2173.05(e)) or includes a typographical error.
An antecedent basis does not exist for:
claim 23, line 3, “the first lower circuit pattern” (term introduced in claims 4, 11, and 21);
claim 23, line 10, “the first lower thickness” (term introduced in claims 4, 11, and 21);
claim 23, lines 10 ~ 11, “the second lower thickness” (term introduced in claims 5, 11, and 21);
claim 23, line 11, “the third lower circuit pattern”; and
claim 23, line 11, “the third lower thickness” (term introduced in claims 6 and 21).
Typographical errors:
claim 1, line 2, replace “thickness” with “thicknesses”;
claim 1, line 5, replace “thickness” with “thicknesses”; and
claim 22, line 3, “.” (period) missing. See MPEP § 608.01(m), Fressola v. Manbeck, 36 USPQ2d 1211 (D.D.C. 1995).
Appropriate correction is required.
Claim Rejections – 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 23, line 4 recites, inter alia, “a first terminal pattern and a second terminal pattern”. The recitation renders claim 23 indefinite in meaning and scope because even after reviewing the specification, the public would not be informed of the metes and bounds of claim 23. Moreover, the recitation is amenable to multiple plausible constructions because the relationship, e.g., independent or related, between the recited portion and earlier appearing elements is not definite. See line 8 of independent claim 1. Additionally, lines 5-6 of claim 23 describe “a first lower terminal pattern, a first upper terminal pattern”. Are the elements described in lines 5-6 different than the elements introduced in line 10 of claim 1? Lastly, lines 6-7 of claim 23 recite “a second lower terminal pattern, a second upper terminal pattern”. See lines 10-11 of claim 1. Applicants are reminded that claims with uncertain boundaries, i.e., claims that are not precise, clear, correct, and unambiguous, fail to inform the public of what constitutes infringement of the claim. Claim 23 has been interpreted in view of the specification without improperly importing limitations from the specification into the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-15, and 21-23 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Song et al. (US 20200373213; below, “Song” – 18 APR 2024 IDS noted reference).
RE 1, Song, in FIGS. 1A, 1B, 2C, 15, and related text, Abstract, paragraphs [0037] to [0049], and [0066], discloses a semiconductor module, comprising:
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a first substrate (17) having a plurality of patterns (171a, 171b) having two or more different thickness [sic] (FIG. 1A, [0044]);
a first semiconductor device (11) disposed on at least one or more patterns (171b);
a second substrate (16) having a plurality of patterns (164) having two or more different thickness [sic] (FIG. 1A, [0044]), wherein one or more of the plurality of patterns (164) of the second substrate (16) is placed on the first semiconductor device (11);
a first terminal pattern (14c, e.g., [0045] and distal part of 161 connected to left-side 12) and a second terminal pattern (14c and distal part of 161 connected to right-side 12), each disposed between the first substrate (17) and the second substrate (16), wherein the first terminal pattern comprises a first upper terminal pattern (distal part of 161) and a first lower terminal pattern (14c), and the second terminal pattern comprises a second upper terminal pattern (distal part of 161) and a second lower terminal pattern (14c); and
a conductive frame (12) coupled (FIG. 1A) to at least one of the first (14c) and the second (distal part of 161) terminal patterns (FIG. 1A).
Thus, Song anticipates this claim.
RE 2, Song discloses the semiconductor module of claim 1, wherein the conductive frame (12) includes:
a first branch (121) electrically connected to at least one of the first upper terminal pattern (distal part of 161) and the first lower terminal pattern (14c); and
a second branch (122) having one end connected to one end of the first branch (121) and the other end extending to the outside of the first and second substrates (17 and 16, respectively).
RE 4, Song discloses the semiconductor module of claim 1, further comprising:
a first lower circuit pattern (171a, 171b) with a first lower thickness being formed on the first substrate (17); and
a first upper circuit pattern (164) with a first upper thickness being formed in a region corresponding to the first lower circuit pattern on the second substrate (16),
wherein the first semiconductor device (11) is coupled (e.g., [0039]) to the first lower circuit pattern (171a, 171b) through a first lower conductive bonding member (14a, 14b), and coupled to the first upper circuit pattern (164) through a first upper conductive bonding member (13).
RE 5, Song discloses the semiconductor module of claim 4, further comprising:
a second lower circuit pattern (171b) with a second lower thickness being formed on the first substrate (17);
a second upper circuit pattern (164) with a second upper thickness being formed in a region corresponding to the second lower circuit pattern (171b) on the second substrate (16); and
a second semiconductor device (11) being disposed between (e.g., [0046]) the second lower circuit pattern (171b) and the second upper circuit pattern (164), and having a first surface (111, The Office notes that an absolute reference frame is not claimed.), on which a first electrode (113) is formed, connected to the second upper circuit pattern (164), and having a second surface (112), on which a second electrode (114) is formed, connected to the second lower circuit pattern (171b),
wherein the second semiconductor device (11) is coupled to the second lower circuit pattern (171b) through a second lower conductive bonding member (14), and coupled to the second upper circuit pattern (164) through a second upper conductive bonding member (13), and
wherein the conductive frame (12) is coupled to the first lower terminal pattern (14c) through a third lower conductive bonding member (e.g., 14a, [0044]), and coupled to the first upper terminal pattern (distal part of 161) through a third upper conductive bonding member (13) ([0039]).
RE 6, Song discloses the semiconductor module of claim 1, further comprising:
a lower conductive dummy pattern (171 flanked by 171b) with a third lower thickness being formed on the first substrate (17); and
an upper conductive dummy pattern (161 between chips 11) with the third upper thickness being formed in a region corresponding to the lower conductive dummy pattern on the second substrate (16),
wherein the lower conductive dummy pattern and the upper conductive dummy pattern are coupled to each other through a fourth conductive bonding member (13).
RE 7, Song discloses the semiconductor module of claim 1, further comprising:
a lower conductive dummy pattern (171 flanked by 171b) with a fourth thickness being formed between the first substrate (17) and the second substrate (16).
RE 8, Song discloses the semiconductor module of claim 1, further comprising:
a molding member (18, e.g., [0045]), the molding member being formed between the first substrate (17) and the second substrate (16).
RE 9, Song discloses the semiconductor module of claim 1, wherein the first substrate (17) and the second substrate (16) are formed of an insulating material, and a heat dissipation layer (e.g., [0041], [0042]) is formed on a second surface of each of the first substrate (17) and the second substrate (16).
RE 10, Song discloses the semiconductor module of claim 1, further comprising:
a first heat dissipation substrate (h1, e.g., FIG. 1B, [0043]), the first heat dissipation substrate (h1) being placed on the first substrate (17) opposite to the plurality of patterns (171a, 171b); and
a second heat dissipation substrate (h2, e.g., FIG. 1B), the second heat dissipation substrate (h2) being placed on the second substrate (16) opposite to the plurality of patterns (161, 164).
RE 11, Song, in FIGS. 1A, 1B, 2C, 15, and related text, Abstract, paragraphs [0037] to [0049], [0066], discloses a semiconductor module, comprising:
a first substrate (17) having a first lower circuit pattern (171a) with a first lower thickness and a second lower circuit pattern (171b) with a second lower thickness different from the first lower thickness, the first lower circuit pattern and the second lower circuit pattern being formed on a first surface of the first substrate (17);
a second substrate (16) disposed to face the first surface of the first substrate (17), and having a first upper circuit pattern (161) with a first upper thickness and a second upper circuit pattern (164) with a second upper thickness, the first upper circuit pattern being formed in a region corresponding to the first lower circuit pattern (171a) on a first surface of the second substrate (16) and the second upper circuit pattern (164) being formed in a region corresponding to the second lower circuit pattern (171b) on the first surface of the second substrate (16);
a first semiconductor device (11) disposed between the first lower circuit pattern (171a) and the first upper circuit pattern (161), and having a first surface (112, The Office notes that an absolute reference frame is not claimed.), on which a first electrode (113) is formed, electrically connected (FIG. 2C) to the first lower circuit pattern (171a), and a second surface (111), on which a second electrode (114) is formed, electrically connected to the first upper circuit pattern (161); and
a second semiconductor device (11) disposed between the second lower circuit pattern (171b) and the second upper circuit pattern (164), and having a first surface (111), on which the first electrode (114) is formed, electrically connected (FIG. 2C, e.g., [0039]) to the second upper circuit pattern (164), and a second surface (112), on which the second electrode (113) is formed, electrically connected to the second lower circuit pattern (171b).
Thus, Song anticipates this claim.
RE 12, Song discloses the semiconductor module of claim 11, wherein
the first semiconductor device (11) is coupled to the first lower circuit pattern (171a) through a first lower conductive bonding member (14a), and coupled to the first upper circuit pattern (161) through a first upper conductive bonding member (13); and
the second semiconductor device (11) is coupled to the second lower circuit pattern (171b) through a second lower conductive bonding member (14), and coupled to the second upper circuit pattern (164) through a second upper conductive bonding member (13).
RE 14, Song discloses the semiconductor module of claim 11, further comprising a plurality of first semiconductor devices (e.g., [0046]) and a plurality of second semiconductor devices (e.g., [0046]), wherein
the first lower circuit pattern (171a) is formed for each of the plurality of first semiconductor devices and the second lower circuit pattern (171b) is formed for each of the plurality of second semiconductor devices on the first substrate (17), and
the first upper circuit pattern (161) is formed for each of the plurality of first semiconductor devices ([0046]) and the second upper circuit pattern (164) is formed for each of the plurality of second semiconductor devices ([0046]) on the second substrate (16).
RE 15, Song discloses the semiconductor module of claim 11, wherein each of the first and second semiconductor devices includes a power semiconductor device ([0038]).
RE 21, Song discloses the semiconductor module of claim 1, wherein the plurality of patterns (171a, 171b) of the first substrate (17) comprises:
a first lower circuit pattern (171a) with a first lower thickness being on the first substrate (17); and
a second lower circuit pattern (171b) with a second lower thickness being on the first substrate (17);
wherein the first semiconductor device (11) is coupled to the first lower circuit pattern (171a), wherein the first lower terminal pattern (14c) is separated from the first lower circuit pattern (171a), and wherein a third lower thickness of the first lower terminal pattern (14c) is different from the first lower thickness of the first lower circuit pattern (171a).
RE 22, Song discloses the semiconductor module of claim 21, wherein a third lower thickness of the first lower terminal pattern (14c) is smaller than the first lower thickness of the first lower circuit pattern (171a) [sic]
RE 23, insofar as definite, Song discloses the semiconductor module of claim 1, further comprising:
a first upper circuit pattern (161) with a first upper thickness being formed in a region corresponding to the first lower circuit pattern (171a) on the second substrate (16), a first terminal pattern (14c) and a second terminal pattern (14c), each disposed between the first substrate (17) and the second substrate (16), wherein the first terminal pattern (14c) comprises a first lower terminal pattern (14c), a first upper terminal pattern (distal part of 161), and the second terminal pattern (14c) comprises a second lower terminal pattern, a second upper terminal pattern;
wherein a lateral width of the first semiconductor device (11) is coupled to a lateral width of the first lower circuit pattern (171a) and a lateral width of the first upper circuit pattern (161), and wherein the first lower thickness of the first lower circuit pattern (171a) is greater than the second lower thickness of the third lower circuit pattern, and the third lower thickness of the first lower terminal pattern (14c) is smaller than the first lower thickness of the first lower circuit pattern (171a) and is greater than the second lower thickness of the third lower circuit pattern.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows (Graham Factors):
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Song. At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 13, Song is silent regarding the semiconductor module of claim 11, wherein the first electrode includes a gate electrode and a source electrode electrically separated from the gate electrode, the second electrode includes a drain electrode, and the drain electrode of the first semiconductor device (11) and the source electrode of the second semiconductor device (11) are electrically connected.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of Song wherein the first electrode includes a gate electrode and a source electrode electrically separated from the gate electrode, the second electrode includes a drain electrode, and the drain electrode of the first semiconductor device and the source electrode of the second semiconductor device are electrically connected, as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As evidence, Song’s [0038] teaches that chip 11 may be various types of components, e.g., MOSFET. Creating a series connection between MOSFETs meets the claimed limitation (e.g., [0046]).
Claim 3 is rejected under 35 U.S.C. 103 as obvious over Song with evidence from or in view of PRAJUCKAMOL et al. (US 20220199502; below, “PRAJ” – 18 APR 2024 IDS noted reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 3, Song is silent regarding the semiconductor module of claim 2, wherein the conductive frame (12) further includes: a connection branch formed as an inclined surface having a first inclination, and having one end connected to the first branch and the other end connected to the second branch.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of Song wherein the conductive frame further includes: a connection branch formed as an inclined surface having a first inclination, and having one end connected to the first branch and the other end connected to the second branch, as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As evidence, see PRAJ’s connection branch (28, 30) of FIG. 1 and related text, e.g., [0042].
Claims 1-15 and 21-23 are rejected.
Conclusion
The prior art made of record and not relied upon, Park et al. (US 20210265235), is considered pertinent to applicants’ disclosure. Park et al. does not teach, inter alia, a first terminal pattern and a second terminal pattern, each disposed between the first substrate (120) and the second substrate (130), wherein the first terminal pattern comprises a first upper terminal pattern and a first lower terminal pattern, and the second terminal pattern comprises a second upper terminal pattern and a second lower terminal pattern; and a conductive frame coupled to at least one of the first and the second terminal patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Parker, can be reached at (571) 272-2298. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815