DETAILED ACTION
This Office action responds to the patent application no. 18/233,296 filed on August 11, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “a surface 101a” as described in the paragraph (¶) [0023] and “hybrid copper bonds or microbump bonds” in the ¶ [0021] in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “a surface 101a” in ¶ [0024]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “hybrid copper bonds or microbump bonds” in the ¶ [0021]. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a hybrid copper bond or a microbump bond” and “a high-bandwidth memory is stacked on the first memory die” must be shown or the feature(s) canceled from the claims 7, 13, 4, and 15. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, and 12 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kim et al. (Kim hereinafter) (US 11,309,228).
Regarding Claims 1, 2, 4, 5, and 12:
Kim (see FIGs. 1, 11, and 16) teaches {1} a device 10/13, comprising: a logic die 110 comprising a first surface; a high-bandwidth memory die 102a/102b located on the first surface at a first predetermined location; and a first memory die 102a/102b located on the first surface at a second predetermined location that is different from the first predetermined location; {2} the first memory die comprises a read-only memory (ROM), a random access memory (RAM), a non-volatile memory, or a combination thereof; {4} the first memory die comprises a random access memory (RAM), and wherein a high-bandwidth memory is stacked on the first memory die; {5} the first memory die comprises a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND flash memory, a NOR flash memory, a single or a multi-level phase-change memory (PCM), a resistive memory (ReRAM), a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor- based memory, a spin-transfer torque MRAM (STT-MRAM), or a combination thereof; {12} the logic die comprises at least one of a central processing unit (CPU) and an accelerator.
Kim (see col.3/ll.60-64, col.4/ll.53-59, col.11/ll.47-57, col.13/ll.57-62 ) teaches “first semiconductor device 110 may include a first electronic product such as a logic semiconductor device … at least one second semiconductor device 120a, 120b may include a second electronic product such as a memory device”; “the second semiconductor device(s) 120a, 102b may include a non-volatile memory device such as DRAM, NAND flash memory, etc. … may include a plurality of stacked semiconductor chips. The number, sizes, locations, etc. of the stacked chips … need not be limited thereto”, “the second semiconductor device(s) 120a, 102b may include a high bandwidth memory (HBM) device … may include a buffer die 121a and first to third memory dies 121b, 121c, 121d sequentially stacked on one another”; “logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (Aps), or the like, and volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 11,309,228) as applied to claim 2 above, and further in view of Zhao et al. (Zhao hereinafter) (US 2021/0335414).
Regarding to Claim 3:
Kim does not explicitly teach the first memory die comprises at least one of a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Zhao (see ¶ [0068]) teaches “other platform components 1350 may include common computing elements, additional memory units … Examples of memory units or memory devices may include without limitation various types of computer readable and machine readable storage media in the form of one or more high speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), …. Programmable ROM (PROM), erasable programmable ROM (EPROM), … flash memory …”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kim to further include the teaching of Zhao to integrate any other memory devices/dies, such as programmable ROM with the logic die and HBM stack to meet the circuit design intended for a packaged semiconductor device.
Claims 6-8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 11,309,228) as applied to claim 1 above, and further in view of Lin et al. (Lin hereinafter) (US 2021/0050300).
Regarding to Claims 6-8, 10, and 11:
Kim does not explicitly teach {6} a second memory die located on the first surface at a third predetermined location that is different from the first predetermined location and the second predetermined location; {7} at least one electrical connection between the logic die and at least one of the high-bandwidth memory, the first memory die and the second memory die comprises a hybrid copper bond or a microbump bond; {8} at least one of the first memory die and the second memory die comprises a read-only memory (ROM), a random access memory (RAM), a non- volatile memory, or a combination thereof; {10} at least one of the first memory die and the second memory die comprises at least one of a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM); and {11} at least one of the first memory die and the second memory die comprises a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND flash memory, a NOR flash memory, a single or multi-level phase- change memory (PCM), a resistive memory (ReRAM), a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor-based memory, a spin-transfer torque MRAM (STT-MRAM), or a combination thereof.
Lin (see FIGs. 39 and 41B and ¶ [0583], [0671], [0719]) teaches 3 small chips stacked with 1 larger chip, such as 1 large multiple high-bandwidth-memory (HBM) integrated-circuit (IC) chip 251 stacked with 1 small non-volatile memory (NVM) IC chip 250 with 1 small FPGA IC chip 200 and with 1 small cooperating and supporting (CS) integrated-circuit (IC) chip 411; or 1 large logic integrated-circuit (IC) chip 326 with 1 small cooperating and supporting (CS) integrated-circuit (IC) chip 411 and with 1 small non-volatile memory (NVM) IC chip 250 and “each of the HBM IC chips 251 … may be … DRAM … SRAM … MRAM … RRAM”; “Each of its microbump or micro-pillars 34”; and “logic integrated-circuit (IC) chips 362, such as FPGA IC chip, … GPU … CPU … DSP”; “its logic integrated-circuit (IC) chip 326 may have … micro-bumps or micro-pillars 34 … each bonded to a metal pads 597, such as copper pad”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kim to further include the teaching of Lin to integrate three small dies on one large die to consolidate the dies for smaller overall package device and to utilize copper bond or microbump bond technique to interconnect between dies for signal transmission.
Claim(s) 13-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 11,309,228) in view of Lin et al. (Lin hereinafter) (US 2021/0050300).
Regarding Claims 13-15 and 17-19:
Kim (see FIGs. 1, 11, and 16) teaches {13} a device 10/13, comprising: a logic die 110 comprising a first surface; a high-bandwidth memory die 102a/102b located on the first surface at a first predetermined location; and a first memory die 102a/102b located on the first surface at a second predetermined location; {14} at least one of the first memory die and the second memory die comprises a read-only memory (ROM), a random access memory (RAM), a non-volatile memory, or a combination thereof; {15} the first memory die comprises a random access memory (RAM), and wherein a high-bandwidth memory is stacked on the first memory die; {17} at least one of the first memory die and the second memory die comprises a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM); {18} at least one of the first memory die and the second memory die comprises a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND flash memory, a NOR flash memory, a single or a multi-level phase-change memory (PCM), a resistive memory (ReRAM), a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor- based memory, a spin-transfer torque MRAM (STT-MRAM), or a combination thereof; {19} the logic die comprises at least one of a central processing unit (CPU) and an accelerator.
Kim (see col.3/ll.60-64, col.4/ll.53-59, col.11/ll.47-57, col.13/ll.57-62 ) teaches “first semiconductor device 110 may include a first electronic product such as a logic semiconductor device … at least one second semiconductor device 120a, 120b may include a second electronic product such as a memory device”; “the second semiconductor device(s) 120a, 102b may include a non-volatile memory device such as DRAM, NAND flash memory, etc. … may include a plurality of stacked semiconductor chips. The number, sizes, locations, etc. of the stacked chips … need not be limited thereto”, “the second semiconductor device(s) 120a, 102b may include a high bandwidth memory (HBM) device … may include a buffer die 121a and first to third memory dies 121b, 121c, 121d sequentially stacked on one another”; “logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (Aps), or the like, and volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like”.
However, Kim does not explicitly teach {13} at least one electrical connection between the first memory die and the logic die comprises a hybrid copper bond or a microbump bond; a second memory die located on the first surface at a third predetermined location that is different from the first predetermined location and the second predetermined location, at least one electrical connection between the second memory die and the logic die comprises a hybrid copper bond or a microbump bond.
Lin (see FIGs. 39 and 41B and ¶ [0583], [0671], [0719]) teaches 3 small chips stacked with 1 larger chip, such as 1 large multiple high-bandwidth-memory (HBM) integrated-circuit (IC) chip 251 stacked with 1 small non-volatile memory (NVM) IC chip 250 with 1 small FPGA IC chip 200 and with 1 small cooperating and supporting (CS) integrated-circuit (IC) chip 411; or 1 large logic integrated-circuit (IC) chip 326 with 1 small cooperating and supporting (CS) integrated-circuit (IC) chip 411 and with 1 small non-volatile memory (NVM) IC chip 250 and “each of the HBM IC chips 251 … may be … DRAM … SRAM … MRAM … RRAM”; “Each of its microbump or micro-pillars 34”; and “logic integrated-circuit (IC) chips 362, such as FPGA IC chip, … GPU … CPU … DSP”; “its logic integrated-circuit (IC) chip 326 may have … micro-bumps or micro-pillars 34 … each bonded to a metal pads 597, such as copper pad”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kim to further include the teaching of Lin to integrate three small dies on one large die to consolidate the dies for smaller overall package device and to utilize copper bond or microbump bond technique to interconnect between dies for signal/data transmission.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 11,309,228) in view of Lin et al. (Lin hereinafter) (US 2021/0050300) as applied to claim 8 or 13 above, and further in view of Zhao et al. (Zhao hereinafter) (US 2021/0335414).
Regarding to Claims 9 and 16:
Kim does not explicitly teach at least one of the first memory die and the second memory die comprises at least one of a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Zhao (see ¶ [0068]) teaches “other platform components 1350 may include common computing elements, additional memory units … Examples of memory units or memory devices may include without limitation various types of computer readable and machine readable storage media in the form of one or more high speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), …. Programmable ROM (PROM), erasable programmable ROM (EPROM), … flash memory …”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kim in the device of Lin to further include the teaching of Zhao to integrate any other memory devices/dies, such as programmable ROM with the logic die and HBM stack to meet the circuit design intended for a packaged semiconductor device.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814