DETAILED ACTION
This action is responsive to the application No. 18/233,486 filed on August 14, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-14, in the reply filed on October 6, 2025, is acknowledged. Claims 15-20 are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a laser scribing line (claim 1), forming a structure at the rear surface of the semiconductor substrate (claim 4), a triangular shape, a pentagonal shape, a semicircular shape, and a semielliptical shape (claim 13), attaching an auxiliary substrate to the front surface of the semiconductor substrate; and forming a metal pattern at the rear surface of the semiconductor substrate, attaching an expanding tape to the rear surface of the semiconductor substrate, and separating the auxiliary substrate between the forming of the lower trench and the forming of the laser scribing line (claim 14), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-3 and 8-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites in the BEOL process, an upper trench is formed at a region overlapping the laser scribing line. This limitation, as best understood, has no written description support because this language implies when the upper trench is formed in the BEOL process, it is overlapping an already present laser scribing line. According to the specification and Fig. 4, when the BEOL process is performed (S1) there is no laser scribing line present (formed later in S8).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites a semiconductor chip splitting method using a laser, comprising: performing a back-end-of-line (BEOL) process comprising forming wiring at or above a front surface of a semiconductor substrate; forming a lower trench at a rear surface of the semiconductor substrate ;forming a laser scribing line on the semiconductor substrate along a region overlapping the lower trench; and splitting the semiconductor substrate into chips by a process comprising cutting along the laser scribing line. First, with respect to the claimed forming wiring “at or above” a front surface of a semiconductor substrate, the “at” option is unclear since applicant only shows forming the wiring above the surface, it is unclear what is required or excluded by the claimed “at” alternative, especially in light of the next line of the claim “forming a lower trench at a rear surface”. According to this language, Applicant uses the term “at” to mean “in” or “into” to describe the disposition of the trench 402 with respect to the rear surface, however none of the wiring is formed “in” or “into” the front surface. Next the claim recites “forming a laser scribing line on the semiconductor substrate along a region overlapping the lower trench”. This limitation is unclear as to where and how this line is formed. There is no “laser scribing line” recited in the detailed description1 making it unclear which feature(s) Applicant regards as the laser scribing line or if this refers to an imaginary line where Applicant intends to subsequently laser scribe the substrate (also note §112 rejections of claim 2). Applicant discloses scribing lines 11, however these are not shown in any cross sections while there are several features overlapping the lower trench 204, e.g. 501, 401, 10, 11, parts of 301 and 303, etc. The recited “on” the semiconductor substrate implies a feature formed on, over, or above a surface of the substrate as one would recite forming a layer on a substrate. The reformed portion 501 formed in (or inside or within, etc.) the substrate is not understood to be formed “on” the substrate. In light of this it is unclear what Applicant regards as the “laser scribing line on the semiconductor substrate”. Claim 1 recites “a semiconductor chip splitting method using a laser….and splitting the semiconductor substrate into chips by a process comprising cutting along the laser scribing line”, which implies the splitting step uses the laser, further noting claims 8 and 9 refer to “the laser”, thus the preamble providing antecedence is given patentable weight at claim 8, however claim 1 does not recite any step of actually using a laser in the body of the claim making it unclear which step(s) use a laser and according to the specification, the chip splitting step S9 is a conventional tape expansion step that does not use a laser.
Claim 2 recites in the BEOL process, an upper trench is formed at a region overlapping the laser scribing line, and is indefinite because this language implies when the upper trench is formed, it is overlapping an already present laser scribing line, which has not been formed yet (see Fig. 4: S1 and S8). When the BEOL process is performed (S1) there is no laser scribing line (S8). It is unclear what sequence Applicant intends to claim since as best understood, the claim language appears to suggest an alternative sequence.
Claim 4 recites “forming a structure at the rear surface”. The only structures shown are the lower trenches and an “align key”. It is unclear what Applicant regards as a structure and what structure is formed or if the trenches, or corners or sidewalls of dies, or a portion of the dicing grid, etc., are supposed to be the structure.
Claim 7 recites “…cutting with a blade, cutting with a saw…”. Forming a trench by cutting with a [saw] blade is understood to be the same well-known process as cutting with a saw [blade]. When alternatives are recited, they are understood to be different, however it is unclear how these alternatives are supposed to be different in the context of claim 7. As best understood, if one is forming a trench by cutting with a blade, this refers to using a conventional dicing saw or similar equipment that uses a saw blade and forming a trench by cutting with a saw is understood to refer to the same process.
Claim 14 recites “performing a backside process of the semiconductor substrate”. It is unclear what Applicant intends by performing a process of the substrate. It is also unclear what the claimed process is and what it does, and what is required by a process. A process could be construed as anything, including viewing/observing the substrate, placing the substrate on something, exposing the backside to air, etc. It is unclear what Applicant regards as a backside process and when a backside process is performed, thus making it unclear when infringement occurs.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-8, and 13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Chuang et al. (US 2022/0399234).
(Re Claim 1) Chuang teaches a semiconductor chip splitting method using a laser, comprising (see Figs. 1-5 and corresponding text):
performing a back-end-of-line (BEOL) process comprising forming wiring at or above a front surface of a semiconductor substrate (¶12-15, Fig. 2, 204 comprises interconnects, semiconductor substrate 100);
forming a lower trench (Fig. 5, 510) at a rear surface of the semiconductor substrate;
forming a laser scribing line (see §112 rejection above, Figs. 1-4, either of 104 or 408) on the semiconductor substrate along a region overlapping the lower trench; and
splitting the semiconductor substrate into chips by a process comprising cutting along the laser scribing line (Fig. 5, laser 504 splits the substrate into chips).
(Re Claim 2) wherein, in the BEOL process (all processes after the initial FEOL processes are considered BEOL), an upper trench (Fig. 3, 310) is formed at a region overlapping the laser scribing line.
(Re Claim 4) wherein the lower trench is formed in a process together with forming a structure at the rear surface of the semiconductor substrate (forming a structure corresponds to forming a right angle at the corners of the dies at the bottom of the trench at the tape when the laser cuts through the substrate in Fig. 5, also see §112 rejection above).
(Re Claim 5) wherein the lower trench is formed in a process together with forming an align key at the rear surface of the semiconductor substrate (as claimed, an align key may be any discernable feature that can be used to align something, including an edge, sidewall, or corner of a feature, in Fig. 5, when the laser cuts through the substrate the combination of sides, edges, and corners of the dies makes an align key).
(Re Claim 6) wherein the lower trench is formed by a process comprising at least one of a physical method, a mechanical method, and a chemical method performed at the rear surface of the semiconductor substrate (a physical method, e.g. laser 504, is used to form the lower trench).
(Re Claim 7) wherein the lower trench is formed through a process comprising at least one of laser irradiation, cutting with a blade, cutting with a saw, wet etching or dry etching (Fig. 5, laser 504).
(Re Claim 8) wherein the laser scribing line is formed by a process comprising irradiating the laser to the semiconductor substrate through the upper trench (Figs. 3-4, wherein the laser scribing line is the trench 408 and is formed by a process wherein a laser 304 is first irradiated to the substrate through the upper trench as shown in Fig. 3, followed by cutting with a dicing blade, the claim language does not preclude a multistep process).
(Re Claim 13) wherein the lower trench comprises a cross-sectional structure having at least one of a quadrangular shape, a triangular shape, a pentagonal shape, a semicircular shape, and a semielliptical shape (Fig. 5: quadrangular).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 2016/0315011) in view of Wakahara et al. (US 2020/0020585).
(Re Claim 1) Ogawa teaches a semiconductor chip splitting method using a laser, comprising (see Figs. 2-5 and 34-36):
performing a back-end-of-line (BEOL) process comprising forming wiring at or above a front surface of a semiconductor substrate (this corresponds to the formation of functional layer F on the front surface, discussed below, ¶¶30,70);
forming a lower trench (Fig. 34, Pd) at a rear surface of the semiconductor substrate;
forming a laser scribing line (Fig. 35, ¶68, Pk) on the semiconductor substrate along a region overlapping the lower trench; and
splitting the semiconductor substrate into chips by a process comprising cutting along the laser scribing line (Fig. 36, Id.).
Ogawa discloses a functional layer F comprising devices and a plurality of insulating layers and notes metal may be included (¶¶30,70) however is silent regarding the inclusion of wiring. A PHOSITA looking for guidance on the formation of a functional layer comprising metal, devices, and insulating layers would be motivated to look to related art to teach details of conventional functional film structures. Related art from Wakahara similarly teaches a wafer having a functional layer 13 comprising insulating layers, metal interconnect wiring, vias, etc. (Fig. 1A and ¶¶ 31-37). In view of Wakahara, a PHOSITA would find it obvious to construct the functional layer F according to Wakahara’s functional layer 13 to provide functional interconnect wiring for the integrated circuit devices present.
(Re Claim 2) wherein, in the BEOL process, an upper trench is formed at a region overlapping the laser scribing line (Figs. 3, 34, upper trench L).
(Re Claim 4) wherein the lower trench is formed in a process together with forming a structure at the rear surface of the semiconductor substrate (forming a structure corresponds to forming a right angle at the corners of the dies, or forming a dicing grid, or alternatively a structure may be the mesas corresponding to each die formed from the backside surface, at trench Pd when the cutting blade 21 cuts the wafer, also see §112 rejection above).
(Re Claim 5) wherein the lower trench is formed in a process together with forming an align key at the rear surface of the semiconductor substrate (as claimed, an align key may be any discernable feature that can be used to align something, including an edge, sidewall, or corner of a feature, when the blade 21 cuts through the substrate, the combination of sides, edges, and corners of the dies makes a grid that can be used as an align key).
(Re Claim 6) wherein the lower trench is formed by a process comprising at least one of a physical method, a mechanical method, and a chemical method performed at the rear surface of the semiconductor substrate (Figs. 11-14, the saw blade 21 is physical and mechanical).
(Re Claim 7) wherein the lower trench is formed through a process comprising at least one of laser irradiation, cutting with a blade, cutting with a saw, wet etching or dry etching (Figs. 11-14, cutting with saw blade 21).
(Re Claim 8) wherein the laser scribing line is formed by a process comprising irradiating the laser to the semiconductor substrate through the upper trench (Fig. 34).
(Re Claim 9) wherein the laser scribing line is in a region in which a portion of the semiconductor substrate is reformed by irradiation of the laser to be converted into a polycrystalline portion or an amorphous portion (Fig. 34, ¶68, modified layer Pk).
(Re Claim 13) wherein the lower trench comprises a cross-sectional structure having at least one of a quadrangular shape, a triangular shape, a pentagonal shape, a semicircular shape, and a semielliptical shape (quadrangular shape).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 2016/0315011) and Wakahara et al. (US 2020/0020585) as applied above, and further in view of Choi et al. (US 2021/0305115).
(Re Claim 3) Ogawa and Wakahara are silent regarding wherein the upper trench is formed by providing a gap fill insulating film after selectively etching and removing a region of a low dielectric constant insulating film and a region of an interlayer insulating film. Ogawa and Wakahara teach forming a trench in the functional layer F/13 comprising low-k and interlayer insulating films. Ogawa forms the trench using a laser which is known to cause damage, debris, and rough surfaces. Related art from Choi teaches etching the layers instead, and then filling the trench with a gap filling insulating layer (Figs. 5-9 and ¶¶31,42-50, trench 164 filled with 172, 182). A PHOSITA would find it obvious to etch the layers and then apply the passivation according to Choi as this process is advantageous since it removes the brittle insulating layers from the dicing regions by etching which results in less damage, debris, and roughness than laser ablation, the removal mitigates cracking and delamination that may occur when dicing, and then passivation is added to protect the exposed surfaces and increase mechanical durability (¶¶52,80).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 2016/0315011) and Wakahara et al. (US 2020/0020585) as applied above, and further in view of Nakamura et al. (US 2006/0281226).
(Re Claim 10) wherein the laser scribing line comprises two lines and forms a split region.
(Re Claim 11) wherein a test element group (TEG) is disposed at the split region.
Ogawa is silent regarding wherein the laser scribing line comprises two lines and forms a split region, and wherein a test element group (TEG) is disposed at the split region. Wakahara discloses when forming the functional layer 13, test element groups (TEG) may be formed in the dicing regions (¶36). TEGs are well known in the art and provide a means for process monitoring and device testing during fabrication and are conventionally placed in dicing lines so they can be easily removed. While Ogawa and Wakahara similarly teach using a laser to cut through the region, related art from Nakamura teaches (see Figs. 5-9) one can use multiple stealth dicing modified regions 24 on either side of the TEG 23 such that the TEG can be singulated along with the dies. This is advantageous since the TEGs can still be used for subsequent analysis instead of being destroyed during dicing, there is less material ablated and redeposited as debris, or in the case of a saw, less material clogging the saw. A PHOSITA would recognize the benefits of using TEGs in dicing lines as taught by Wakahara and Nakamura and the benefits of Nakamura’s process to singulate the TEGs using stealth laser dicing rather than destroying them using laser ablation or other processes.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 2016/0315011), Wakahara et al. (US 2020/0020585) and Nakamura et al. (US 2006/0281226) as applied above and further in view of Choi et al. (US 2021/0305115) and Chuang et al. (US 2022/0399234).
(Re Claim 12) wherein a dam comprising a metal layer comprising the wiring is disposed at sides of the laser scribing line.
Ogawa is silent regarding a dam comprising a metal layer comprising the wiring is disposed at sides of the laser scribing line. Related art from Choi teaches forming a dam 116 at the perimeter of each die along the dicing lines (¶35). Related art from Chuang also similarly teaches forming a dam 202 around the perimeter of each die along the dicing lines. These “dam” features are conventionally called crack stops or die seals and are well known in the art, formed along with the multilayer interconnects/ILDs, and are used to prevent moisture and cracks from penetrating into the die regions. A PHOSITA would find it obvious to include dams along the die perimeters as taught by Choi and Chuang to increase yield by preventing cracking and moisture penetration.
Allowable Subject Matter
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 14 recites the allowable subject matter “…further comprising: attaching an auxiliary substrate to the front surface of the semiconductor substrate and performing a backside process of the semiconductor substrate between the BEOL process and the forming of the lower trench; and forming a metal pattern at the rear surface of the semiconductor substrate, attaching an expanding tape to the rear surface of the semiconductor substrate, and separating the auxiliary substrate between the forming of the lower trench and the forming of the laser scribing line”.
None of the prior art known to the Examiner teaches the additional method steps with respect to the required sequence. Related art from Liu et al. (US 9,837,366): Figs. 1A-2J, Masuko (US 2017/0069535): Figs. 4-10, and Chen et al. (US 2021/0375826): Figs. 2A-3D, are pertinent to individual steps recited in claim 14, however none teach the additional steps recited in claim 14 with respect to the required sequence.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related dicing methods involving forming trenches, filling trenches with insulating layers, various backside processes including forming metal, alignment marks, stealth dicing, crack stops/seal rings, and the use of auxiliary substrates and tapes at various stages of the process.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
1 It is noted the term only appears in the original claims and in ¶7 which is essentially a copy of claim 1.