Prosecution Insights
Last updated: April 19, 2026
Application No. 18/233,628

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED FERROELECTRIC MEMORY ELEMENTS AND METHOD OF MAKING THE SAME

Non-Final OA §102
Filed
Aug 14, 2023
Examiner
WARREN, MATTHEW E
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandisk Technologies LLC
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
862 granted / 986 resolved
+19.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to the Election filed on November 26, 2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on November 26, 2025 is acknowledged. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention there being no allowable generic or linking claim. Election was made without traverse in the reply. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sondhi et al. (US Pub. 2024/0064991 A1). The applied reference has a common inventor (or assignee) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. In re claim 1, Sondhi et al. shows (fig. 21D) a semiconductor memory device, comprising: an alternating stack of insulating layers (32) and electrically conductive layers (46B); a memory opening (58) vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel (60) and a vertical stack of discrete ferroelectric material portions (154) located at levels of the electrically conductive layers, wherein the discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers (32). In re claim 2, Sondhi et al. shows (fig. 21D) a first discrete ferroelectric material portion of the discrete ferroelectric material portions comprises an outer sidewall that is in direct contact with a cylindrical sidewall of a first electrically conductive layer of the electrically conductive layers, and an inner sidewall adjoined to the outer sidewall; and an entirety of the inner sidewall is spaced by a first distance from a most proximal point within an interface between the first electrically conductive layer and the outer sidewall. In re claim 3, Sondhi et al. shows (fig. 21D)wherein the inner sidewall comprises: a cylindrical surface segment; an upper convex annular surface segment that is adjoined to a top periphery of the cylindrical surface segment; and a lower convex annular surface segment that is adjoined to a bottom periphery of the cylindrical surface segment. In re claim 14, Sondhi et al. shows (fig. 21D) the vertical stack of discrete ferroelectric material portions is in direct contact with cylindrical surface segments of the insulating layers. Allowable Subject Matter Claims 4-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bae et al. (US Pub. 2023/0180481 A1), Nam (US 12,464,727 B2), Takekida (WO-2023105763-A1), and Li (CN-112652630-A) also disclose various elements of the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Aug 14, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604765
INTEGRATED PASSIVE DEVICE DIES AND METHODS OF FORMING AND PLACEMENT OF THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604545
PHOTO DIODE WITH DUAL BACKSIDE DEEP TRENCH ISOLATION DEPTH
2y 5m to grant Granted Apr 14, 2026
Patent 12593455
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593453
FERROELECTRIC MEMORY DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12588271
MULTI-LAYER ELECTRODE TO IMPROVE PERFORMANCE OF FERROELECTRIC MEMORY DEVICE
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.6%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allow rate.

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