DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-17 & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US 20220037497).
Regarding claim 1, Chung discloses that a three-dimensional field-effect transistor (3DSFET) device comprising:
a 1st source/drain region 228DS (Fig. 14A-C); and
a 2ⁿᵈ source/drain region 248SD (Fig. 14AC)stacked on the 1st source/drain region, wherein the 1st source/drain region 228SDhas a protrusion at a 2ⁿᵈ upper corner portion among a 1st upper corner portion and the 2ⁿᵈ upper corner portion opposite to each other in a channel- width direction view (Fig. 14B-C, see modified Fig. 14C below).
PNG
media_image1.png
717
416
media_image1.png
Greyscale
Reclaim 2, Chung discloses that the protrusion is formed on around a center of a top surface of the 1st source/drain region, in a channel-length direction view (Fig. 14A-14C).
Reclaim 3, Chung discloses that the 2ⁿᵈ upper corner portion is in a shape in which the 2ⁿᵈ upper corner portion is protruded in at least a vertical direction, in both the channel-width direction view and a channel-length direction view (Fig. 14A-14C).
Reclaim 4, Chung discloses that the 2ⁿᵈ upper corner portion is protruded in a horizontal direction, in the channel-width direction view (Fig. 14A-14C).
Reclaim 5, Chung discloses that the 2ⁿᵈ upper corner portion is protruded in a diagonal direction, in the channel-width direction view (Fig. 14A-14C).
Reclaim 6, Chung discloses that the 2ⁿᵈ upper corner portion is in a shape in which the 2ⁿᵈ upper corner portion is protruded in at least a horizontal direction, in the channel-width direction view (Fig. 14A-14C).
Reclaim 7, Chung discloses that the protrusion comprises p-type impurities or n-type impurities(Fig. 14A-14C).
Reclaim 8, Chung discloses that a contact structure 234/236 connected to the protrusion (Fig. 14A-C).
Reclaim 9, Chung discloses that a width of the 2ⁿᵈ source/drain region 248SD is smaller than a width of the 1st source/drain region 228SD, in a channel-width direction view, and wherein the protrusion is not vertically overlapped by the 2ⁿᵈ source/drain region (Fig. 14A-C).
Regarding claim 10, Chung discloses that a three-dimensional field-effect transistor (3DSFET) device comprising:
a 1st source/drain region 128SD (Fig. 14A-14C); and
a 2ⁿᵈ source/drain region 248SD stacked above the 1st source/drain region 228SD, wherein the 1st source/drain region 228SED has a deformed shape at a 2ⁿᵈ upper corner portion among a 1st upper corner portion and the 2nd upper corner portion opposite to each other, in a channel-width direction view (Fig. 14B-C, note: a deformed shape is not clearly defined yet, therefore, Chung’s element 228SD is considered as a deformed shape).
Reclaim 11, Chung discloses that the 1st source/drain region has a greater height at the 2ⁿᵈ upper corner portion than at the 1st upper corner portion, in the channel- width direction view.
Reclaim 12, Chung discloses that the 1st source/drain region has a greater width at a top surface portion than at a bottom surface portion, in the channel-width direction view.
Reclaim 13, Chung discloses that the 1st source/drain region has a greater width at a top surface portion than at a bottom surface portion, in the channel-width direction view.
Reclaim 14, Chung discloses that the 1st source/drain region has a protrusion on around a center of a top surface of the 1st source/drain region, in a channel-length direction view.
Reclaim 15, Chung discloses that the 2ⁿᵈ upper corner portion comprises p-type impurities or n-type impurities.
Regarding claim 16, Chung discloses that a method of manufacturing three-dimensional field-effect transistor (3DSFET) device, the method comprising:
forming, on a substrate 202, a 1st source/drain region 228SD and a 2ⁿᵈ source/drain region 248SD above the 1st source/drain region 228SD (Fig. 14A-C); and
structuring the 1st source/drain region 228SD such that the 1st source/drain region has a protrusion at a 2ⁿᵈ upper corner portion among a 1st upper corner portion and the 2ⁿᵈ upper corner portion opposite to each other in a channel-width direction view (see modified Fig. 14C above).
Reclaim 17, Chung discloses that a width of the 2ⁿᵈ source/drain region is smaller than a width of the 1st source/drain region, in the channel-width direction view, and wherein the protrusion is not vertically overlapped by the 2ⁿᵈ source/drain region.
Reclaim 20, Chung discloses that the protrusion of the structured 1st source/drain region is in an extended shape in a vertical direction, a horizontal direction and a diagonal direction, in the channel-width direction view (Fig. 14A-C).
Allowable Subject Matter
Claims 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SU C KIM/Primary Examiner, Art Unit 2899