Prosecution Insights
Last updated: April 19, 2026
Application No. 18/233,697

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME

Non-Final OA §102§103§112
Filed
Aug 14, 2023
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Western Digital Technologies Inc.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
95%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allow Rate
628 granted / 912 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+26.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
52 currently pending
Career history
964
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
34.3%
-5.7% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
36.0%
-4.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 912 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of group I, species I(c), claims 1-10, in the reply filed on February 5, 2026 is acknowledged. Claims 11-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 5, 2026. Claim 7 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. There is no support in the elected embodiment of Fig. 63 for the claim limitations of "a metal oxide blocking dielectric layer located between the first electrically conductive layers and the first metal oxide etch stop layer", as recited in claim 7, and this feature is found on unelected embodiment of Fig. 75B. Information Disclosure Statement The information disclosure statements (IDS) submitted on August 29, 2023 and May 31, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first lateral extent’, “horizontal plane” and “second lateral extent” (claim 9) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a) because they fail to show “150” ([0136]) as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “44” has been used to designate both “outer blocking dielectric layer” and “metal oxide blocking dielectric layer”; and reference character “80” has been used to designate both “opening” and “layer contact via cavities”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: 1) Undefined acronyms/symbols, such as “CF4”, “CHF4” ([0112]); “BCl3” (0113]). The examiner suggests that applicant spell out all the acronyms/symbols when using them for the first time in the disclosure; and 2) Typographical error. “Glass(i.e” should read “glass (i.e” ([0116]). Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 4-6 and 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of "horizontal and vertical portions of the first stepped surfaces", as recited in claim 4, is unclear as to whether said limitation is in one-to-one or multiple-to-one between the horizontal and vertical portion(s) and the first stepped surface applicant refers. Claims 6 and 8-10 recite the limitation "the first metal oxide etch stop layer". There is insufficient antecedent basis for this limitation in the claims. Also, it is unclear as to whether said limitation is the same as or different from “at least one first metal oxide etch stop layer”, as recited in claim 1 and/or “a continuous first metal oxide etch stop layer”, as recited in claim 4. Claims 6 and 10 recite the limitation "the layer contact via structure". There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an electrically conductive layer contact via structure”, as recited in claim 1. Claim 8 recites the limitation "the horizontal surfaces". There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different form “horizontal and vertical portions of the first stepped surfaces”, as recited in claim 4. The claimed limitation of "the horizontal surfaces of the first electrically conductive layers", as recited in claim 8, is unclear as to whether said limitation is in one-to-one or multiple-to-one between the horizontal surface and the first electrically conductive layer applicant refers. The claimed limitation of "a horizontal plane", as recited in claim 9, lines 6 and 12, is unclear as to whether said limitation is the same as or different from "a horizontal plane", as recited in claim 9, line 4. The claimed limitation of "the first lateral extent is less than the second lateral extent", as recited in claim 9, is unclear as to what dimension of the first lateral extent is less than what dimension of the second lateral extent applicant refers. The claimed limitation of "a lateral extend", as recited in claim 9, line 9, is unclear as to whether said limitation is the same as or different from "a second lateral extent", as recited in claim 9, line 6. The claimed limitation of "… a lateral extent … is greater than the first lateral extent", as recited in claim 9, is unclear as to what dimension of a lateral extent … is greater than what dimension of the first lateral extent applicant refers. The claimed limitation of "a bottom surface", as recited in claim 9, lines 13-14, is unclear as to whether said limitation is the same as or different from "a bottom surface", as recited in claim 9, lines 4-5. The claimed limitation of "a bottommost layer", as recited in claim 9, line 14, is unclear as to whether said limitation is the same as or different from "a bottommost layer", as recited in claim 9, line 5. The claimed limitation of "an opening", as recited in claim 9, line 15, is unclear as to whether said limitation is the same as or different from "a memory opening", as recited in claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, as best understood, is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhang et al. (2023/0069420). As for claim 1, Zhang et al. show in Fig. 2, 4A, 4B (or 4C) and related text a semiconductor structure 400, comprising: a first alternating stack of first insulating layers 452 and first electrically conductive layers 498, the first alternating stack having first stepped surfaces 464; at least one first metal oxide etch stop layer 468 overlying and contacting the first stepped surfaces; a first stepped dielectric material portion 470 overlying the at least one first metal oxide etch stop layer and the first stepped surfaces; a memory opening 336 vertically extending through the first alternating stack; a memory opening fill structure 337/338/339/462 located in the memory opening and comprising a memory film 337 and a vertical semiconductor channel 338 ([0100]-[0104]); and an electrically conductive layer contact via structure 214 vertically extending through the first stepped dielectric material portion and the at least one first metal oxide etch stop layer, and contacting a respective one of the first electrically conductive layers ([0109]). As for claim 2, Zhang et al. show the at least one first metal oxide etch stop layer comprises at least one first transition-metal oxide layer ([0096]). As for claim 3, Zhang et al. show the at least one first transition-metal oxide layer comprises at least one of hafnium oxide or zirconium oxide ([0096]). As for claim 4, Zhang et al. show the at least one first metal oxide etch stop layer comprises a continuous first metal oxide etch stop layer which contacts both horizontal and vertical portions of the first stepped surfaces (Fig. 4A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-6 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rha et al. (2022/0216227) in view of Zhang et al. (2023/0069420). Rha et al. show in Fig. 3A (or 3B), 6A and related text: As for claims 1-4, a semiconductor structure 10I, comprising: a first alternating stack GS1 of first insulating layers 120 and first electrically conductive layers GS2 ([0036]), the first alternating stack having first stepped surfaces (lower portion of) SR1; a first stepped dielectric material portion 190 overlying the first stepped surfaces; a memory opening vertically extending through the first alternating stack; a memory opening fill structure CH located in the memory opening and comprising a memory film 145 and a vertical semiconductor channel 140 (Fig. 3A or 3B; [0072]-[0076]); and an electrically conductive layer contact via structure CNT vertically extending through the first stepped dielectric material portion and contacting a respective one of the first electrically conductive layers. As for claim 5, a second alternating stack GS2 of second insulating layers 220 and second electrically conductive layers 230 overlying the first alternating stack ([0036]), the second alternating stack having second stepped surfaces (middle portion of) SR1; and a second stepped dielectric material portion overlying the second stepped surfaces 290 (Fig. 6A). As for claim 6, the second alternating stack overlies the first alternating stack; the second stepped dielectric material portion overlies the first stepped dielectric material portion; the memory opening vertically further extends through the second alternating stack; and the layer contact via structure further vertically extends through the second stepped dielectric material portion (Fig. 6A). As for claim 9, a first insulating cap layer 125 located between the first alternating stack and the second alternating stack; wherein: the memory opening has a first lateral extent at a horizontal plane including a bottom surface of a bottommost layer of the second alternating stack; the memory opening has a second lateral extent at a horizontal plane including a top surface of the first insulating cap layer; the first lateral extent is less than the second lateral extent (Fig. 6A). As for claim 10, a third alternating stack GS3 of third insulating layers 320 and third electrically conductive layers 330 having third stepped surfaces (upper portion of) SR1 and overlying the second alternating stack; and a third stepped dielectric material portion 390 overlying the second stepped surfaces, wherein: the memory opening further vertically extends through the third alternating stack; and the layer contact via structure further vertically extends through the third stepped dielectric material portion (Fig. 6A). Rha et al. do not disclose at least one first metal oxide etch stop layer overlying and contacting the first stepped surfaces; the first stepped dielectric material portion overlying the at least one first metal oxide etch stop layer (claim 1); the at least one first metal oxide etch stop layer comprises at least one first transition-metal oxide layer (claim 2); the at least one first transition-metal oxide layer comprises at least one of hafnium oxide or zirconium oxide (claim 3); the at least one first metal oxide etch stop layer comprises a continuous first metal oxide etch stop layer which contacts both horizontal and vertical portions of the first stepped surfaces (claim 4); the first metal oxide etch stop layer further overlies the first alternating stack; the second alternating stack overlies the first metal oxide etch stop layer; the memory opening vertically further extends through the first metal oxide etch stop layer (claim 6); the first metal oxide etch stop layer directly contacts the horizontal surfaces of the first electrically conductive layers in the first stepped surfaces (claim 8); the memory opening fill structure has a lateral extent at a level of the first metal oxide etch stop layer which is greater than the first lateral extent; the memory opening fill structure has an annular horizontal surface within a horizontal plane including a top surface of the first metal oxide etch stop layer; the annular horizontal surface is in contact with an annular segment of a bottom surface of a bottommost layer within the second alternating stack; and the memory film is in contact with a sidewall of an opening through the first metal oxide etch stop layer (claim 9); a second metal oxide etch stop layer overlying the second alternating stack; the third alternating stack overlying the second metal oxide etch stop layer; the memory opening vertically further extends through the first metal oxide etch stop layer (claim 10). Zhang et al. show in Fig. 2, 4A, 4B (or 4C) and related text: As for claims 1, 6, 9 and 10, at least one first metal oxide etch stop layer 468 overlying a first metal oxide etch stop layer (topmost one of) 452 and the stack (rest of) 452/498 and contacting stepped surfaces 464; the stepped dielectric material portion 470 overlying the at least one first metal oxide etch stop layer; the memory opening 336 vertically through the first metal oxide etch stop layer; the memory opening fill structure 337/338/339/462 has a lateral extent at a level of the first metal oxide etch stop layer; the memory opening fill structure has a lateral extent at a level of the first metal oxide etch stop layer; the memory film 337 is in contact with a sidewall of an opening through the first metal oxide etch stop layer. As for claim 2, the at least one first metal oxide etch stop layer comprises at least one first transition-metal oxide layer ([0096]). As for claim 3, the at least one first transition-metal oxide layer comprises at least one of hafnium oxide or zirconium oxide ([0096]). As for claim 4, the at least one first metal oxide etch stop layer comprises a continuous first metal oxide etch stop layer which contacts both horizontal and vertical portions of the first stepped surfaces (Fig. 4A). As for claim 8, the first metal oxide etch stop layer directly contacts the horizontal surfaces of the first electrically conductive layers in the first stepped surfaces (Fig. 4A). Rha et al. and Zhang et al. are analogous art because they are directed to a memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Rha et al. with the specified feature(s) of Zhang et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include at least one metal oxide etch stop layer overlying and contacting stepped surfaces of each stack, wherein the at least one first metal oxide etch stop layer comprising at least one first transition-metal oxide layer; the at least one first transition-metal oxide layer comprising at least one of hafnium oxide or zirconium oxide; the at least one first metal oxide etch stop layer comprising a continuous first metal oxide etch stop layer which contacts both horizontal and vertical portions of the first stepped surfaces, as taught by Zhang et al., in Rha et al.'s device, in order to in order to improve drive current and to protect the IC surface from mechanical damage and ionic contamination. Therefore, the combined device shows: As for claim 6, the second alternating stack overlies the first metal oxide etch stop layer; the memory opening vertically further extends through the second alternating stack, and through the first metal oxide etch stop layer. As for claim 9, the memory opening fill structure has a lateral extent at a level of the first metal oxide etch stop layer which is greater than the first lateral extent; the memory opening fill structure has an annular horizontal surface within a horizontal plane including a top surface of the first metal oxide etch stop layer; the annular horizontal surface is in contact with an annular segment of a bottom surface of a bottommost layer within the second alternating stack; and the memory film is in contact with a sidewall of an opening through the first metal oxide etch stop layer. As for claim 10, a second metal oxide etch stop layer overlying the second alternating stack; a third alternating stack of third insulating layers and third electrically conductive layers having third stepped surfaces and overlying the second metal oxide etch stop layer; wherein: the memory opening further vertically extends through the third alternating stack and through the second metal oxide etch stop layer; and the layer contact via structure further vertically extends through the third stepped dielectric material portion and the second metal oxide etch stop layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Aug 14, 2023
Application Filed
Feb 26, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
95%
With Interview (+26.0%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 912 resolved cases by this examiner. Grant probability derived from career allow rate.

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