DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on 03/06/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SANO et al. (US 2016/0322374 A1).
As to claim 1, SANO et al. disclose in Fig. 15 a three-dimensional memory device, comprising:
an alternating stack of insulating layers (32) and electrically conductive layers {46/(46A/46B/46C/46D/46E/46F)} (Fig. 15, para. [0087], [0094]);
an array of memory openings (see an opening having element 55, Fig. 15, para. [0151]) vertically extending through the alternating stack (Fig. 15, para. [0151]); memory-opening-free areas (“contact region” 300) located in the array of the memory openings in a plan view (Fig. 15, para. [0147]-[0148]); an array of memory opening fill structures (“memory stack structures” 55) located in the array of memory openings (see an opening having element 55, Fig. 15, para. [0151]), wherein each of the memory opening fill structures (“memory stack structures” 55) comprises a respective vertical semiconductor channel (60) and respective memory elements located at levels of the electrically conductive layers {46/(46A/46B/46C/46D/46E/46F)} (Fig. 15, [0190], [0203]); and layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15) located within the memory-opening-free areas in the plan view (Fig. 15, para. [0191], [0201], [0212]), wherein each of the layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15) comprises a respective layer contact via structure (66/66A/66B/66B/66C/66D/66E/66F) contacting a respective one of the electrically conductive layers {46/(46A/46B/46C/46D/46E/46F)} and further comprises a respective insulating spacer (64) that laterally surrounds the respective layer contact via structure (66/66A/66B/66B/66C/66D/66E/66F) (Fig. 15, para. [0187], [0191]).
As to claim 2, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein the layer contact via structures (66/66A/66B/66B/66C/66D/66E/66F) comprise at least one row of layer contact via structures (66/66A/66B/66B/66C/66D/66E/66F) that are arranged along a first horizontal direction and laterally spaced from each other by subarrays of memory opening fill structures (55), and wherein each of the subarrays includes a respective subset of the array of memory opening fill structures (55) (Fig. 15).
As to claim 3, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein: each of the memory opening fill structures further comprises a respective drain region (63) contacting a top end of the respective vertical semiconductor channel (60) (para. [0204]); the three-dimensional memory device (Fig. 15) further comprises bit lines (para. [0130], [0143], [0204]) laterally spaced apart from each other along a first horizontal direction and laterally extending along a second horizontal direction; each of the bit lines (para. [0130], [0143], [0204]) is electrically connected to a respective subset of the drain regions (63) (Fig. 15, para. [0130], [0143], [0204]).
As to claim 9, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein: the alternating stack (32, 46) comprises a pair of lengthwise sidewalls that laterally extend along a first horizontal direction and vertically extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack (Fig. 15); and the memory-opening-free areas (300) comprise a column of memory-opening-free areas (300) laterally extending from one of the pair of lengthwise sidewalls to another of the pair of lengthwise sidewalls (Fig. 15).
As to claim 10, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein: the alternating stack (32, 46) comprises a pair of lengthwise sidewalls that laterally extend along a first horizontal direction and vertically extend from a bottommost layer of the alternating stack (32, 46) to a topmost layer of the alternating stack; and the array of memory-opening-free areas (300) is laterally spaced from a lengthwise sidewall of the pair of lengthwise sidewalls by at least one row of memory opening fill structures (55) that is a subset of the array of memory opening fill structures (55) that laterally extends along the first horizontal direction (Fig. 15).
As to claim 11, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the memory device further comprising drain-select-level dielectric isolation structures (62) laterally extending along a first horizontal direction, and vertically extending through at least one electrically conductive layer (46) including a topmost electrically conductive layer (46A) within the alternating stack (32, 46).
As to claim 12, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein: wherein: the layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15) comprise a row of layer contact assemblies that are arranged along first horizontal direction; and the row of layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15) is laterally spaced from at least one row of memory opening fill structures (55) within the array of memory opening fill structures (55) by one of the drain-select-level dielectric isolation structures (62) (Fig. 15).
As to claim 13, as applied to claim 1 above, SANO et al. disclose in Fig. 15 all claimed limitations including the limitation: wherein:the layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15) comprise a row of layer contact assemblies that are arranged along first horizontal direction; and one of the drain-select-level dielectric isolation structures (62) extends through an upper portion of each layer contact assembly within the row of layer contact assemblies (comprising 66/66A/66B/66B/66C/66D/66E/66F & 64, Fig. 15).
Allowable Subject Matter
Claims 4-8 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 31, 2026
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