DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
2. Claim 1 is objected to because of the following informalities:
In claim 1, line 1, “pixel circuitry” should be changed to “a pixel circuitry”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1 – 6, 13 – 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOO et al. (2023/0035054).
With regard to claim 1, KOO et al. disclose a display panel (for example, see paragraph [0034], fig. 8A) comprising;
a substrate (for example, paragraph [0201]) and pixel circuitry (a pixel circuitry having transistors T1 – T5 forming in the pixel groups PX11, PX12, PX13) disposed on the substrate (for example, paragraph [0201]),
wherein the pixel circuitry comprises a plurality of transistor groups (transistors T1 – T5) and a plurality of signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3),
each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) comprises a power supply signal line (PL_T1) and a first data signal line (D2) both extending in a first direction (DR2), the plurality of transistor groups (transistors T1 – T5) are divided into a plurality of transistor group columns (transistor columns as being defined as the direction DR2, for forming the pixels PX11, PX12, PX13 or transistor columns as being defined in the top view for forming the pixels PX11, PX12, PX13; for example, see paragraphs [0065], [0093], [0094]) by the signal line groups (D2, D3, D4, PL_T1, PL_T2, PL_T3), each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) is disposed between two adjacent ones of the transistor group columns (transistor columns as being defined as the direction DR2, for forming the pixels PX11, PX12, PX13 or transistor columns as being defined in the top view for forming the pixels PX11, PX12, PX13; for example, see paragraphs [0065], [0093], [0094]), and each of the transistor groups (transistors T1 – T5) is disposed between two adjacent ones of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3); and
in each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3), a width (referred to as “W1” by examiner’s annotation shown in fig. 8A below) of the power supply signal line (PL_T1) is greater than a width (referred to as “W2” by examiner’s annotation shown in fig. 8A below) of the first data signal line (D2), the power supply signal line (PL_T1) at least partially overlaps the first data signal line (D2) inherently in a thickness direction of the display panel (for example, see paragraph [0034], fig. 8A), a part of the power supply signal line (PL_T1) overlapping the first data signal line (D2) is provided with at least one through hole (referred to as “H1” by examiner’s annotation shown in fig. 8A below; or referred to as “H2” by examiner’s annotation shown in fig. 8A below, wherein the opening H2 functioning as a hole), and the first data signal line (D2) overlaps the through hole (H1 or H2) inherently in the thickness direction.
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With regard to claim 2, KOO et al. disclose each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) further comprises a second data signal line (D1 or D3), and in each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3), the second data signal line (D1) and the first data signal line (D2) are arranged side by side in parallel, and the second data signal (D1 or D3) line does not overlap the power supply signal line (PL_T1) inherently in the thickness direction.
With regard to claim 3, KOO et al. disclose the first data signal line (D2) and the second data signal line (D1 or D3) respectively in every two adjacent ones of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) are inherently configured to drive ones (one of transistors T2, T4, T5 T6; for example, paragraph [0081]) of the transistor groups (transistors T1 – T5) respectively in different rows each being in a second direction (DR1, because the first and second data lines D1, D2, or D3 forming in a whole cross -sectional pixel area) perpendicular to the first direction (DR2), the first data signal line (D2) and the second data signal line (D1 or D3) in each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) are inherently configured to drive ones (one of transistors T2, T4, T5 T6; for example, paragraph [0081]) of the transistor groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3) in a same row in the second direction (DR1), and each of the transistor groups is coupled to one of the first data signal line (D2) and the second data signal line (D1 or D3).
With regard to claim 4, KOO et al. disclose the first data signal line (D2) is straight, and the power supply signal line (PL_T1) is not straight.
With regard to claim 5, KOO et al. disclose the power supply signal line (PL_T1) comprises a first segment (referred to as “A1” by examiner’s annotation shown in fig. 8A below) and a second segment (referred to as “A2” by examiner’s annotation shown in fig. 8A below) both extending in the first direction (DR2), and a third segment (referred to as “A3” by examiner’s annotation shown in fig. 8A below) connected between the first segment (A1) and the second segment (A2), the first segment (A1) being not aligned with the second segment (A2), and in each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3), the first segment (A1) overlaps the first data signal line (D2) inherently in the thickness direction, the through hole (H1) is disposed in the first segment (A1), and the second segment (A2) does not overlap the first data signal line (D2) inherently in the thickness direction.
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With regard to claim 6, KOO et al. disclose the through hole (H2 as indicated above) extends in the first direction (DR2).
With regard to claim 13, KOO et al. disclose the first data signal line (D2) is straight, and the power supply signal line (PL_T1) is not straight.
With regard to claim 14, KOO et al. disclose the power supply signal line (PL_T1) comprises a first segment (referred to as “A1” by examiner’s annotation shown in fig. 8A below) and a second segment (referred to as “A2” by examiner’s annotation shown in fig. 8A below) both extending in the first direction (DR2), and a third segment (referred to as “A3” by examiner’s annotation shown in fig. 8A below) connected between the first segment (A1) and the second segment (A2), the first segment (A1) being not aligned with the second segment (A2), and in each of the signal line groups (D1, D2, D3, D4, PL_T1, PL_T2, PL_T3), the first segment (A1) overlaps the first data signal line (D2) inherently in the thickness direction, the through hole (H1) is disposed in the first segment (A1), and the second segment (A2) does not overlap the first data signal line (D2) inherently in the thickness direction.
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With regard to claim 15, KOO et al. disclose the through hole (H2 as indicated above) extends in the first direction (DR2).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 7 – 9, 16 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOO et al. (2023/0035054) in view of Yu et al. (2022/0310750).
With regard to claims 7, 16, KOO et al. do not clearly disclose a width of the through hole in a second direction perpendicular to the first direction is greater than the width of the first data signal line.
However, Yu et al. disclose a width (referred to as “D1” by examiner’s annotation shown in fig. 9 below) of the through hole (50) in a second direction (a horizontal direction) perpendicular to the first direction (a vertical direction) is greater than the width (referred to as “D2” by examiner’s annotation shown in fig. 9 below) of the first data signal line (981). (for example, see fig. 9).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KOO et al.’s device to have a width of the through hole in a second direction perpendicular to the first direction is greater than the width of the first data signal line as taught by Yu et al. in order to reduce a line width of metal wirings for shrinking the size of a light-emitting element, shrinking the size of a transistor and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 8, 17, KOO et al. do not clearly disclose a distance between two outermost edges of the first segment away from the through hole in a second direction perpendicular to the first direction is greater than a width of the second segment.
However, Yu et al. disclose a distance (referred to as “D3” by examiner’s annotation shown in fig. 9 below) between two outermost edges of the first segment (referred to as “91A” by examiner’s annotation shown in fig. 9 below) away from the through hole (50) in a second direction (DR1) perpendicular to the first direction (DR2) is greater than a width of the second segment (referred to as “D4” by examiner’s annotation shown in fig. 9 below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KOO et al.’s device to have a distance between two outermost edges of the first segment away from the through hole in a second direction perpendicular to the first direction is greater than a width of the second segment as taught by Yu et al. in order to reduce a line width of metal wirings for shrinking the size of a light-emitting element, shrinking the size of a transistor and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 9, 18, KOO et al. do not clearly disclose the display panel has a layer structure comprising: an active layer disposed on the substrate, the active layer comprising semiconductor layers respectively corresponding to a plurality of thin film transistors; a first metal layer disposed on a side of the active layer away from the substrate, wherein the first metal layer comprises a source, a drain, and the power supply signal line, and the source and the drain are at least electrically connected to one of the semiconductor layers corresponding to one of the thin film transistors; a first insulating layer disposed on a side of the first metal layer away from the substrate; and a second metal layer disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising the first data signal line.
However, Yu et al. disclose the display panel has a layer structure comprising: an active layer (for example, see paragraphs [0113], [0133]) disposed on the substrate (40), the active layer comprising semiconductor layers (for example, see paragraphs [0113], [0142], [0133]) respectively corresponding to a plurality of thin film transistors (for example, see paragraph [0134]); a first metal layer (a first source-drain metal layer; for example, paragraph [0133]) disposed on a side of the active layer away from the substrate (40), wherein the first metal layer (a first source-drain metal layer; for example, paragraph [0133]) comprises a source, a drain, and the power supply signal line (the first source-drain metal layer is used for forming the power signal line pattern 91; for example, see paragraph [0137]), and the source and the drain are at least electrically connected to one of the semiconductor layers (for example, see paragraphs [0113], [0142], [0133]) corresponding to one of the thin film transistors (for example, see paragraph [0134]); a first insulating layer (ILD, fig. 17) disposed on a side of the first metal layer away from the substrate (40); and a second metal layer (a second source-drain metal layer; for example, paragraph [0133]) disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising the first data signal line (981). (for example, see paragraph [0138]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KOO et al.’s device to have an active layer disposed on the substrate, the active layer comprising semiconductor layers respectively corresponding to a plurality of thin film transistors; a first metal layer disposed on a side of the active layer away from the substrate, wherein the first metal layer comprises a source, a drain, and the power supply signal line, and the source and the drain are at least electrically connected to one of the semiconductor layers corresponding to one of the thin film transistors; a first insulating layer disposed on a side of the first metal layer away from the substrate; and a second metal layer disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising the first data signal line as taught by Yu et al. in order to reduce the size of the semiconductor device and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claim(s) 10, 11, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOO et al. (2023/0035054) in view of Yu et al. (2022/0310750) and further in view of Jeon et al. (11217652).
With regard to claims 10, 19, KOO et al. and Yu et al. do not clearly disclose a material of the first metal layer is same as that of the second metal layer, and a thickness of the first metal layer is greater than a thickness of the second metal layer.
However, Jeon et al. disclose a material (copper material; for example, column 11, lines 29, 30) of the first metal layer (M1) is same as that material (copper material; for example, column 11, lines 45, 46) of the second metal layer (M2), and a thickness (6800 angstroms; for example, column 11, lines 34, 35) of the first metal layer (M1) is greater than a thickness (4500 angstroms; for example, column 11, lines 45 - 48) of the second metal layer (M2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KOO et al. and Yu et al.’s device to have a material of the first metal layer is same as that of the second metal layer, and a thickness of the first metal layer is greater than a thickness of the second metal layer as taught by Jeon et al. in order to increase response speeds of the device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claims 11, 20, Jeon et al. disclose the first metal layer (M1) comprises a laminate of titanium-layer/aluminum-layer/titanium-layer (for example, column 11, lines 32 – 34). Jeon et al. disclose a thickness of the first metal layer M1, including the aluminum-layer, may be about 4,500 Å to about 9,000 Å, but do not disclose a thickness of the aluminum-layer is greater than or equal to 7000 angstroms. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a thickness of the aluminum-layer is greater than or equal to 7000 angstroms because a prima facie case of obviousness exists where the claimed ranges and prior art ranges overlap that one skilled in the art would have expected them to have the same properties. Moreover, the Federal Circuit informs us that a prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art. In re Peterson, 65 USPQ2d 1379, 1382 (Fed. Cir 2003) citing In re Geisler, 116 F.3d 1465, 1469, 43 USPQ2d 1362, 1365 (Fed. Cir. 1997); In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936-37 (CCPA 1976); and In re Malagari, 499 F.2d 1297, 1303, 182 USPQ 549, 553 (CCPA 1974). See MPEP § 2144.05.
8. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOO et al. (2023/0035054) in view of Yu et al. (2022/0310750) and further in view of CHENG et al. (2023/0337466).
With regard to claim 12, KOO et al. disclose a width of a part of the first segment (A1) on either side of the through hole (H1) in a second direction (DR1) perpendicular to the first direction (DR2).
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KOO et al. and Yu et al. do not clearly disclose a width of a part of the first segment is greater than or equal to 1.9 microns.
However, CHENG et al. disclose a width of a part of the power line 240, including any segment, functioning as the first segment, is 5 microns (5 microns > 1.9 microns). (for example, see paragraph [0139], fig. 4D).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KOO et al. and Yu et al.’s device to have a width of a part of the first segment is greater than or equal to 1.9 microns as taught by CHENG et al. in order to reduce a line width of metal wirings for shrinking the size of a light-emitting element, shrinking the size of a transistor and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812