DETAILED ACTION/EXAMINERS’ COMMENT
This Office action responds to the amendments filed on 01/27/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 01/27/2026 in reply to the non-final rejection mailed on 10/28/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 17 is cancelled. Accordingly, pending in this Office action are claim 1-5, 9-16, & 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 9-16, & 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu (US 20230307421).
Regarding Claim 1, Yu (see, e.g., fig. 3) shows a multi-die package on package, comprising:
a bottom package 10a (see, e.g., para.0043) comprising
a first device die 50 (see, e.g., para.0045)
and a second device die 801 (see, e.g., para.0046)
wherein the first device die is an application processor die (see, e.g., para.0045)
and the second device die is an image signal processor die or a modem die (see, e.g., para.0046)
and a top package 20 (see, e.g., para.0053) comprising
a memory die 210 (see, e.g., para.0053),
stacked on the bottom package.
Regarding Claim 2, Yu shows the multi-die package on package according to claim 1,
wherein the bottom package comprises
a first substrate 100 (see, e.g., para.0034) having a top surface 100a
and a bottom surface opposite to the top surface 100b.
Regarding Claim 3, Yu shows the multi-die package on package according to claim 2,
wherein the first substrate comprises
a re-distribution layer (RDL) substrate (see, e.g., para.0044)
or
an organic substrate.
Regarding Claim 4, Yu shows the multi-die package on package according to claim 2,
wherein the first substrate comprises
a first dielectric layer 112 (see, e.g., para.0054)
and a first interconnect structure 110a-d (see, e.g., para.0054) surrounded by the first dielectric layer,
wherein the first interconnect structure comprises
a plurality of ball pads 110b (see, e.g., para.0062) on the bottom surface for connection with solder balls.
Regarding the limitation “a plurality of ball pads… for connection with solder balls,” Examiner interprets the limitation as functional language that merely recites the intended use or function of the plurality of balls pads. The functional language is not directed to the structure of the plurality ball pads, or the presence of solder balls, rather to the capability of connection with solder balls, and thus does not carry patentable weight. In re Schreiber, 128 F.3d at 1478, 44 USPQ2d at 1432; In re Swinehart, 439 F.2d 210, 213, 169 USPQ 226, 228 (CCPA 1971) ("where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on")
Additionally, were the limitation to carry patentable weight, Yu (see, e.g., fig. 3, para.0062) teaches solder balls 120 connected to the plurality of ball pads 110b.
Regarding Claim 5, Yu shows the multi-die package on package according to claim 4,
wherein the first device die 50 and the second device die 801 are disposed on the top surface of the first substrate in a side-by-side manner (see, e.g., fig. 3),
and wherein the first device die is electrically connected to the second device die through the first interconnect structure of the first substrate (para.0046).
Regarding Claim 9, Yu shows the multi-die package on package according to claim 2 further comprising:
at least one passive element 130 (see, e.g., para.0041) disposed on the bottom surface of the first substrate.
Regarding Claim 10, Yu shows the multi-die package on package according to claim 9,
wherein the at least one passive element 130 comprises
an integrated passive device (IPD) (see, e.g., para.0041)
or
a multi-layer ceramic capacitor (MLCC).
Regarding Claim 11, Yu shows the multi-die package on package according to claim 4 further comprising:
an encapsulant SM (see, e.g., para.0038) on the top surface of the first substrate.
Regarding Claim 12, Yu shows the multi-die package on package according to claim 11,
wherein the encapsulant surrounds the first device die (see, e.g., fig. 3).
Regarding Claim 13, Yu shows the multi-die package on package according to claim 11 further comprising:
a plurality of through vias 60 (see, e.g., para.0040) disposed around the first device die on the top surface of the first substrate.
Regarding Claim 14, Yu shows the multi-die package on package according to claim 13 further comprising:
a second substrate 300 (see, e.g., para.0038) disposed on the through vias and on the encapsulant.
Regarding Claim 15, Yu shows the multi-die package on package according to claim 14,
wherein the second substrate comprises
a re-distribution layer (RDL) substrate (see, e.g., para.0037)
or
an interposer substrate (see, e.g., para.0037).
Regarding Claim 16, Yu shows the multi-die package on package according to claim 14,
wherein the second substrate comprises
a second dielectric layer 312 (see, e.g., para.0037)
and a second interconnect structure 310 (see, e.g., para.0037),
wherein the second structure is electrically connected to the first interconnect structure of the first substrate through the through vias (see, e.g., para.0038).
Regarding Claim 20, Yu shows the multi-die package on package according to claim 1,
wherein the first device die (see, e.g., para.0055) and the second device die have different sizes (see, e.g., fig. 3).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 9-16, & 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2818
Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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