Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-11, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US PGPub 2023/0157027).
Claim 1: Chen teaches a three-dimensional (3D) memory device comprising a memory plane (Fig. 1), wherein the memory plane comprises: a first edge (edge with dummy region); and an array of blocks (Fig. 1;[0058-0059]) comprising: a plurality of memory blocks configured to store data [0058-0059]), wherein the plurality of memory blocks are separated by continuous slit structures (108); and a first dummy region (106/506) (Fig. 8) between the first edge and the plurality of memory blocks, the first dummy region comprising alternating first slit structures (550) and second slit structures (slit connecting dummy channels 112), wherein the first slit structures and the second slit structures are discontinuous slit structures (Fig. 8).
Claim 2: Chen teaches (Fig. 7, 8) the first dummy region comprises one to four dummy blocks.
Claim 3: Chen teaches (Fig. 7, 8) each dummy block comprises two of the first slit structures, and wherein one or more of the second slit structures are between the two first slit structures.
Claim 4: Chen teaches (Fig. 7, 8) the memory plane comprises: a second edge opposite the first edge; and a second dummy region between the second edge and the plurality of memory blocks, the second dummy region comprising alternating first slit structures and second slit structures.
Claim 10: Chen teaches [0059] wherein each slit structure comprises an insulating material.
Claim 11: Chen teaches [0059] the insulating material lines each slit structure.
Claim 17: Chen teaches (Fig. 10) the continuous slit structures electrically isolate the plurality of memory blocks.
Claim 18: Chen teaches a system, comprising: a three-dimensional (3D) memory device (904) comprising a memory plane (Fig. 1), wherein the memory plane comprises: a first edge; and an array of blocks comprising (Fig. 1, [0058-0059]): a plurality of memory blocks configured to store data, wherein the plurality of memory blocks are separated by continuous slit structures (109); and a first dummy region (106/506) (Fig. 8) between the first edge and the plurality of memory blocks, the first dummy region comprising alternating first slit structures (550) and second slit structures (slit connecting dummy channels 112), wherein the first slit structures and the second slit structures are discontinuous slit structures (Fig. 8); and a memory controller (906) electrically connected to the 3D memory device (fig. 19), wherein the memory controller is configured to manage data to and from the 3D memory device [0100-0104].
Claim 19: Chen teaches a (See claims 1 and 8) three-dimensional (3D) memory device comprising a memory plane, wherein the memory plane comprises: a first edge; and an array of blocks comprising: a plurality of memory blocks configured to store data, wherein the memory blocks are separated by continuous slit structures; and one or more dummy blocks between the first edge and the plurality of memory blocks, each dummy block comprising a first slit structure separating adjacent blocks and one or more second slit structures dividing the dummy block into a plurality of fingers, wherein the first slit structure and the one or more second slit structures are discontinuous slit structures.
Claim 20: Chen teaches (Fig. 2) the array of blocks comprises one to four dummy blocks.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9, 12-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US PGPub 2023/0157027) as applied to claim 1 above, and further in view of Lee (US PGPub 2022/0157726).
Regarding claim 5, as described above, Chen substantially reads on the invention as claimed, except Chen does not teach wherein each memory block is divided into a plurality of fingers by one or more discontinuous slit structures. Lee teaches each memory block is divided into a plurality of fingers by one or more discontinuous slit structures as common in the art (Fig. 2; [0060-0063]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Chen to have had each memory block is divided into a plurality of fingers by one or more discontinuous slit structures as common in the art (Fig. 2; [0060-0063]) as taught by Lee.
Claim 6: Lee teaches (Fig. 11) the array of blocks comprises a staircase structure region between two core array regions as known in the art of vertical channel memory devices.
Claim 7: Lee teaches (Fig. 2) each first slit structure comprises a slit extending across the staircase structure region, and wherein the slit has a length at least greater than a length of the staircase structure region.
Claim 8: Lee teaches (Fig. 2) the array of blocks comprises a core array region between two staircase structure regions.
Claim 9: Lee teaches [0072] each block comprises alternating layers of an oxide and layers of tungsten, and wherein, for each discontinuous gate slit structure comprising alternating slits and spaces, each space comprises the alternating layers of the oxide and layers of tungsten.
Claim 12: Lee teaches [0062] the insulating material comprises at least one of an oxide, carbon, or polysilicon. Oxide is a well known and obvious insulator material choice.
Claim 13: Lee teaches [0072] each slit structure is filled with a filling material.
Claim 14: Lee teaches [0072] the filling material comprises a conductive material.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US PGPub 2023/0157027), as applied to claim 1 above, and further in view of Lee et al. (US PGPub 2017/0170191).
Regarding claim 15, as described above, Chen substantially reads on the invention as claimed, except Chen does not teach each slit of each discontinuous slit structure has a length in a range from 1 micron to 10 microns. Lee (191) teaches the block lengths being between 3.5-10microns, therefore the slits between the blocks would have equivalent length [0048]. Since it has been held when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on ranges by showing unexpected results or the criticality of the claimed range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claim. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F. 2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 716.02-716.02(g) for a discussion of criticality and unexpected results. Therefore, one of ordinary skill in the art would have been able to determine the length range claimed through routine experimentation.
Claim 16: Lee (191) teaches [0048] slits of each discontinuous slit structure are 1 micron to 10 microns apart from one another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARAH K SALERNO/Primary Examiner, Art Unit 2814