DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8-15-2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the convex/concave concept must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Jeng (US 20140217610 A1) and Lin (US 20230074159 A1)
Regarding claim 1, Wang discloses A semiconductor package (Fig. 11) comprising:
a first semiconductor device (110, 120, 130’) comprising a semiconductor chip (120);
an interposer (140) comprising and electrically connected to the first semiconductor device, wherein the first semiconductor device is provided on the interposer;
a second semiconductor device (160); and
a substrate (180), wherein the interposer and the second semiconductor device are provided on the substrate and are spaced apart from each other, wherein the interposer is electrically connected to the second semiconductor device (Fig. 11).
Wang discloses the interposer (140) comprising of metallization layers but is silent to the interposer being a silicon.
Jeng discloses (¶ [0032]) a device package formation wherein using silicon substrates for the interposer may reduce the stress because the coefficient of the thermal expansion (CTE) mismatch between the silicon substrates and the silicon typically used for the dies is lower than with substrates formed of different material.
As such, one of ordinary skill in the art before the filing date of the invention would have substituted the silicon interposer of Jeng for the metal interposer of Wang to avoid induced stress caused by a large mismatch in the coefficient thermal expansion.
Wang discloses dimensions of the first and second device in the side view, but is silent to the dimension of the devices in the plan view. Lin, in the same field of endeavor, discloses (Figs. 1A-B) a first device (120A, Fig. 2B) on interposer (230, 240, Fig. 2C) and a second device (125A, Fig. 2B) on substrate (110A, 290) showing the plan view of the first and second devices (120, 125 respectively, Figs. 1A-B) wherein the y-dimension of the devices are the same. Practitioners in the art would have appreciated application of the same width to the aside devices would allow measurement uniformity, functional design, or aesthetic alignment. Such one of ordinary skill in the art before the effective filing date of the invention would have adopted the design layout of Lin to the package of Wang to achieve measurement uniformity and aesthetic alignment.
The modification of Lin to Wang would result the volume of the first device overlapping the substrate being smaller or equal to that of the second device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply the plan view area of the first package to be the same as that of the second package for the ease of package handling and aesthetic appearance.
Regarding claim 2, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1. Wang discloses (Fig. 11) wherein a first distance between the first semiconductor device and the second semiconductor device, is substantially equal to a second distance between the interposer and the second semiconductor device.
Regarding claim 3, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1. Wang further discloses on an upper surface of the interposer, a plurality of first connection terminals (123, Fig. 5) for an electrical connection to the first semiconductor device are provided, and wherein, under a lower surface of the interposer, a plurality of third connection terminals (150, Fig. 5) for electrical connection to the substrate are provided.
Regarding claim 4, Wang in view of Jeng and Lin discloses the semiconductor package of claim 3; Wang further discloses a plurality of second connection terminals (163, Fig. 10) electrically connecting the second semiconductor device to the substrate, and a pitch (P3) of the plurality of second connection terminals is substantially equal to a pitch (P1) of the plurality of third connection terminals (¶¶ [0050, 0055])
Regarding claim 5, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1. Lin further discloses (Figs. 1A-B) the first shape is substantially the same as the second shape.
Regarding claim 6, Wang in view of Jeng and Lin discloses (Fig. 11) the semiconductor package of claim 1. Wang further discloses an outer edge of the first semiconductor device is substantially the same as an outer edge of the interposer.
Regarding claim 12, Wang in view of Jeng and Lin discloses the semiconductor package of claim 3. While Wang disclosing (Fig. 10, ¶¶ [0050, 0055]) the pitch comparison between substrate/second device and substrate/interposer (P1 vs P3), Wang is silent regarding a pitch of the plurality of first connection terminals is equal to or greater than a pitch of the plurality of third connection terminals, and wherein a width of the plurality of first connection terminals is equal to or greater than a width of the plurality of third connection terminals.
As such where the general conditions (pitch comparison) of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges (pitch of different connection terminals) by routine experimentation. MPEP 2144.05. Thus, one of ordinary skill in the art before the effective filing date of the invention would have opted to select the pitch of the first terminals to be equal or greater than that of the third terminal for better connection reliability.
Regarding claim 13, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1. Wang further discloses comprising (Fig. 9, ¶ [0048]) a molding layer (170, 170’, 170a’) around the first semiconductor device, the second semiconductor device, and the interposer, wherein side surfaces of the second semiconductor device are surrounded by the molding layer, and an upper surface of the second semiconductor device is exposed.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Jeng (US 20140217610 A1), Lin (US 20230074159 A1) and Tseng (US 20140110847 A1)
Regarding claim 11, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1; while Wang is not explicitly disclosing a thermal expansion coefficient of the first semiconductor device is different from a thermal expansion coefficient of the substrate, Wang discloses (¶ [0050]) the construed substrate 180 is formed on encapsulation 170, (¶ [0065]) the first package (chips 110, 120) encapsulated by encapsulation 130, such that encapsulation layers are utilized to support the substrate and the fist package.
Tseng discloses (¶ [0019]) the molding is applied to improve to minimize the stress caused by the mismatch in coefficient of thermal expansion between IC chip and substrate. Thus, as evidenced by Tseng, one of ordinary skill in the art before the effective filing date of the invention would have appreciated thermal expansion mismatch between the first semiconductor device and the substrate based on the disclosure of Wang and Tseng to alleviate internal stress as disclosed by Tseng (¶ [0019]).
As such, it would have been obvious for an ordinary skill in the art before the effective filing date of the invention to realize Wang implicitly discloses the mismatch in the coefficient thermal expansion in the package thru the view of Tseng using encapsulation to address the issue.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Jeng (US 20140217610 A1), (Lin (US 20230074159 A1) and Chen (US 20200006286 A1)
Regarding claim 7, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1, but is silent regarding the first semiconductor device has a convex shape, and the substrate has a concave shape, and wherein the interposer is electrically connected to the first semiconductor device, and is electrically connected to the substrate.
Chen discloses (Fig. 9, ¶ [0031]) a first device (70) has a convex shape and a substrate (80) has a concave shape and an interposer (200, ¶ [0015], Fig. 8) between electrically connected 70 and 80.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have substituted the package of Wang for the convex/concave package of Chen for minimizing the warpage damage caused by the CTE mismatch and improving the connectivity of the solder joints (Chen: ¶¶ [0031, 0033]).
Regarding claim 8, Wang in view of Jeng and Lin discloses the semiconductor package of claim 1, but is silent regarding the semiconductor package of claim 1, wherein the first semiconductor device has a concave shape, and the substrate has a convex shape, and wherein the interposer is electrically connected to the first semiconductor device and the substrate.
Chen discloses (Fig. 17 and ¶ [0043]) a first device (170) has a concave shape, substrate (180) has a convex shape, and interposer connecting 170 to 180 (fan-out package 170 suggesting an interposer disposed between DD and substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have substituted the package of Wang for the convex/concave package of Chen for minimizing the warpage damage caused by the CTE mismatch and improving the connectivity of the solder joints (Chen: ¶¶ [0031, 0033]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Jeng (US 20140217610 A1), Lin (US 20230074159 A1), Chen2 (US 20230317624 A1), and Kurihara (US 20040173914 A1)
Regarding claim 9, Wang in view of Jeng and Lin discloses the package of claim 1 but is silent regarding a curvature of the interposer is less than a curvature of the first device and a curvature of the substrate.
Chen2 discloses (Fig. 5A) an interposer (120) between logic dies (110) and a circuit board or other routing substrate (¶[0019]) and RDL 120 would be made with underlying stiffener structure because without it, RDL 120 can be susceptible to stress induced by bending, thermal expansion.
Kurihara discloses (Fig. 3, ¶ [0049]) discloses coefficient of thermal expansion of interposer 11A is set to a value between the coefficients of thermal expansion of the semiconductor chip 12 and the substrate 13.
Chen2 discloses the interposer to be made stiff to minimize induced stress caused by thermal expansion. Kurihara discloses the thermal expansion coefficient differences between chip package, interposer, and substrate. Such that where the general conditions of a claim (coefficient difference, stiff interposer) are disclosed in the prior arts (Chen2, Kurihara), it is not inventive to discover the optimum (interposer’s thermal expansion coefficient) or workable range by routine experimentation. MPEP 2144.05
Thus, one of ordinary skill in the art before the effective filing date of the invention would have selected the thermal expansion coefficient of interposer to be the smallest of those of the substrate and the first device through routine optimization (stiff material has lower thermal expansion coefficient).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Lin (US 20230074159 A1), Chen2 (US 20230317624 A1), and Kurihara (US 20040173914 A1), and Chen (US 20200006286 A1)
Regarding claim 10, Wang in view of Lin, Chen2, and Kurihara discloses the package of claim 9, and the curvature of the first device and the curvature of the substrate are different from each other but is silent regarding the first device and the substrate have a concave shape or a convex shape.
Chen discloses (Fig. 9, ¶¶ [0031], and Fig. 17, ¶ [0043]) the interposer (70 or 170 respectively) and the substrate (180) have a convex shape and a concave shape to minimize the warpage due to CTE mismatch.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to employ the convex/concave shape of Chen to the package of Wang to avoid warpage damage.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1), Boo (US 20240071990 A1), Val (US 20130171752 A1), and Jeng (US 20140217610 A1)
Regarding claim 14, Wang discloses (Fig. 20, ¶ [0077]) a first printed circuit board substrate (CB) electrically connected to the outside;
a memory package (110, 120, 130’) comprising the first printed circuit board substrate (CB) and memory chips stacked (110, 120) on the first printed circuit board substrate.
Wang (Fig. 20) does not disclose a silicon interposer electrically connected to the first printed board substrate and a logic chip spaced apart from the silicon interposer, wherein the logic chip and the silicon interposer are disposed on a second printed circuit board. However, Wang (Fig. 11) discloses memory package (110, 130, 110’) is disposed on redistribution layer 140 and a logic chip 160 (¶ [0046]) is spaced apart from the redistribution layer 140; the redistribution layer 140 and logic chip 160 are disposed on redistribution layer 180.
Fig. 11 and Fig. 20 of Wang individually discloses the interconnection function of the respective interposer and the PCB to the device. Combining the two would yield the same interconnection support to the device. Such that, it is not inventive to combine equivalents for the same purpose. MPEP 2144.06
Moreover, Boo discloses (Figs. 1A-B, ¶ [0013]) a direct chip attachment assembly that directly attach a chip on a PCB for simplifying connection path of the chip. As such, artisans in the field would have appreciated using a direct chip attachment to a circuit board would yield better electrical connection and integration simplification.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the chip package of Wang Fig. 11 with a direct chip attachment to a circuit board for shortest connection passage. The modification would result for the memory chip to connect to a circuit board then connects to an interposer before being placed on a larger substrate.
The modification of Fig. 11 showing a logic chip (160) spaced apart from the interposer (140) and both the interposer and the logic chip connected to a large redistribution layer (180).
Wang does not disclose a second PCB to which the interposer and the logic chip connected.
Although the emerging use of interposers and redistribution layers in support of chip package interconnection, Val (¶ [0074]) discloses the use of PCB for external connection in stacked packaging is greatly favored. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the redistribution layer of Wang for a PCB to support external connection.
Wang (Fig. 11) discloses the interposer (140) comprising of metallization layers but is silent to the interposer being a silicon.
Jeng discloses (¶ [0032]) a device package formation wherein using silicon substrates for the interposer may reduce the stress because the coefficient of the thermal expansion (CTE) mismatch between the silicon substrates and the silicon typically used for the dies is lower than with substrates formed of different material.
As such, one of ordinary skill in the art before the filing date of the invention would have substituted the silicon interposer of Jeng for the metal interposer of Wang to avoid induced stress caused by a large mismatch in the coefficient thermal expansion.
Regarding claim 15, Wang in view of Boo, Val, and Jeng discloses the modified package of claim 14, Wang further discloses a plurality of first connection terminals (123, Fig. 6) configured to be electrically connected to the first printed circuit board substrate are disposed on an upper surface of the silicon interposer, and wherein a plurality of third connection terminals (150, Fig. 6) configured to be electrically connected to the second printed circuit board substrate are disposed under a lower surface of the silicon interposer.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Boo (US 20240071990 A1), Val (US 20130171752 A1), Jeng (US 20140217610 A1), Huang (US 10886147 B1), and Yang (20230170327 A1)
Regarding claim 18, Wang in view of Boo, Val, and Jeng discloses the modified package of claim 15, but is silent to a first pitch of the first terminals in the range of [100 µm; 200 µm] and a third pitch of the third terminals in the range of [50 µm; 100 µm].
The modified package of Wang does not reveal a first pitch of the first terminal is larger than a third pitch of the third terminals.
Huang discloses (Fig. 5) a package (120e) wherein a pitch (154) between the interposer (160) and the chip package (120, 121, 122, 102, Fig. 1C, col. 3, lines 61-67) is larger than a pitch (192) between the interposer and a substrate (180); and the width of 154 is larger than the width of 192.
One of ordinary skill in the art at before the effective filing date of the invention would have substituted the interposer structure of Huang for the interposer structure of Wang’s modified package for enhancing connectivity and reliable bonding between the chip package and the interposer.
The modified package of Wang in view of Yang and Huang is silent on the ranges of the first pitch and the third pitch.
Yang (¶ [0025]) discloses “… IC dies with micro-bumps have interconnect pitch in a range between 10 microns and 80 microns; IC dies with solder-capped copper pillars have interconnect pitch between 80 microns and 150 microns …”
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to adopt the pitch ranges of Yang to the pitch ranges of Wang’s modified package as its existing ranges of the IC dies. The pitch ranges of the interposer are then adapted to mate with those IC’s to form the interconnection between package components.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of Boo (US 20240071990 A1), Val (US 20130171752 A1), Jeng (US 20140217610 A1), and Chen (US 20200006286 A1)
Regarding claim 16, Wang in view of Boo, Val, and Jeng discloses the modified package of claim 14, but is silent regarding the first and second PCB each have a concave or convex shape.
Chen discloses (Fig. 9, ¶ [0031]) a first device (70) has a convex shape and a substrate (80) has a concave shape and an interposer (200, ¶ [0015], Fig. 8) between electrically connected 70 and 80.
The package 70 of Chen does not include a PCB substrate; however, a PCB substrate can be added to a package for better structure support and system interfacing as disclosed in Wang’s Fig. 20. Thus, a package having a convex shape would result the PCB attached to it having similar shape.
One of ordinary skill in the art before the effective filing date of the invention would have substituted the convex/concave package of Chen for the modified package of Wang for minimizing the warpage damage caused by the CTE mismatch and improving the connectivity of the solder joints (Chen: ¶¶ [0031, 0033]).
Claim(s) 17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of in view of Boo (US 20240071990 A1), Val (US 20130171752 A1), Jeng (US 20140217610 A1), Chen2 (US 20230317624 A1), and Kurihara (US 20040173914 A1)
Regarding claim 17, Wang in view of Yang discloses the modified package of claim 14 and the first and second printed circuit boards having equal or different curvature (which is always true regardless), but is silent to the curvature of the silicon interposer is less than the curvature of the first and second printed circuit board.
Chen2 discloses (Fig. 5A) an interposer (120) between logic dies (110) and a circuit board or other routing substrate (¶ [0019]) and RDL 120 would be made with underlying stiffener structure because without it, RDL 120 can be susceptible to stress induced by bending, thermal expansion.
Kurihara discloses (Fig. 3, ¶ [0049]) discloses coefficient of thermal expansion of interposer 11A is set to a value between the coefficients of thermal expansion of the semiconductor chip package 12 and the printed circuit board substrate 13 (¶ [0033]).
Chen2 discloses the interposer to be made stiff to minimize induced stress caused by thermal expansion. Kurihara discloses the thermal expansion coefficient differences between chip package, interposer, and substrate. Such that where the general conditions of a claim (coefficient difference, stiff interposer) are disclosed in the prior arts (Chen2, Kurihara), it is not inventive to discover the optimum (interposer’s thermal expansion coefficient) or workable range by routine experimentation. MPEP 2144.05
The package 12 of Chen2 does not include a PCB substrate; however, a PCB substrate can be added to a package for better structure support and system interfacing as disclosed in Wang’s Fig. 20. Thus, a package having a PCB attached to it would act as a single package connecting to the interposer and then the external PCB.
Thus, one of ordinary skill in the art before the effective filing date of the invention would have selected the thermal expansion coefficient of interposer to be the smallest of those of the package and the PCB through routine optimization (stiff material has lower thermal expansion coefficient).
Regarding claim 19, Wang discloses (Fig. 20, ¶ [0077]) a first printed circuit board substrate (CB) and a memory package (110, 120, 130’) stacked on the first printed circuit board substrate (CB).
Wang (Fig. 20) does not disclose a silicon interposer electrically connected to the first printed board substrate and a logic chip spaced apart from the silicon interposer, wherein the logic chip and the silicon interposer are disposed on a second printed circuit board. However, Wang (Fig. 11) discloses memory package (110, 130, 110’) is disposed on redistribution layer 140 and a logic chip 160 (¶ [0046]) is spaced apart from the redistribution layer 140; the redistribution layer 140 and logic chip 160 are disposed on redistribution layer 180.
Fig. 11 and Fig. 20 of Wang individually discloses the interconnection function of the respective interposer and the PCB to the device. Combining the two would yield the same interconnection support to the device. Such that, it is not inventive to combine equivalents for the same purpose. MPEP 2144.06
Moreover, Boo discloses (Figs. 1A-B, ¶ [0013]) a direct chip attachment assembly that directly attach a chip on a PCB for simplifying connection path of the chip. As such, artisans in the field would have appreciated using a direct chip attachment to a circuit board would yield better electrical connection and integration simplification.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the chip package of Wang Fig. 11 with a direct chip attachment to a circuit board for shortest connection passage. The modification would result for the memory chip to connect to a circuit board then connects to an interposer before being placed on a larger substrate.
The modification of Fig. 11 showing a logic chip (160) spaced apart from the interposer (140) and both the interposer and the logic chip connected to a large redistribution layer (180).
Wang does not disclose a second PCB to which the interposer and the logic chip connected.
Although the emerging use of interposers and redistribution layers in support of chip package interconnection, Val (¶ [0074]) discloses the use of PCB for external connection in stacked packaging is greatly favored. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the redistribution layer of Wang for a PCB to support external connection.
Wang (Fig. 11) discloses the interposer (140) comprising of metallization layers but is silent to the interposer being a silicon.
Jeng discloses (¶ [0032]) a device package formation wherein using silicon substrates for the interposer may reduce the stress because the coefficient of the thermal expansion (CTE) mismatch between the silicon substrates and the silicon typically used for the dies is lower than with substrates formed of different material.
As such, one of ordinary skill in the art before the filing date of the invention would have substituted the silicon interposer of Jeng for the metal interposer of Wang to avoid induced stress caused by a large mismatch in the coefficient thermal expansion.
The modified package of Wang would include the first and second printed circuit board with equal or different curvature (which is always true regardless) but not include the curvature of the silicon interposer being less than that of the first and second printed circuit boards.
Chen2 discloses (Fig. 5A) an interposer (120) between logic dies (110) and a circuit board or other routing substrate (¶[0019]) and RDL 120 would be made with underlying stiffener structure because without it, RDL 120 can be susceptible to stress induced by bending, thermal expansion.
Kurihara discloses (Fig. 3, ¶ [0049]) discloses coefficient of thermal expansion of interposer 11A is set to a value between the coefficients of thermal expansion of the semiconductor chip package 12 and the printed circuit board substrate 13 (¶ [0033]).
Chen2 discloses the interposer to be made stiff to minimize induced stress caused by thermal expansion. Kurihara discloses the thermal expansion coefficient differences between chip package, interposer, and substrate. Such that where the general conditions of a claim (coefficient difference, stiff interposer) are disclosed in the prior arts (Chen2, Kurihara), it is not inventive to discover the optimum (interposer’s thermal expansion coefficient) or workable range by routine experimentation. MPEP 2144.05
The package 12 of Chen2 does not include a PCB substrate; however, a PCB substrate can be added to a package for better structure support and system interfacing as disclosed in Wang’s Fig. 20. Thus, a package having a PCB attached to it would act as a single package connecting to the interposer and then the external PCB.
Thus, one of ordinary skill in the art before the effective filing date of the invention would have selected the thermal expansion coefficient of interposer to be the smallest of those of the package and the PCB through routine optimization (stiff material has lower thermal expansion coefficient).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230260920 A1) in view of in view of Boo (US 20240071990 A1), Val (US 20130171752 A1), Jeng (US 20140217610 A1), Chen2 (US 20230317624 A1), Kurihara (US 20040173914 A1), Huang (US 10886147 B1), and Lin (US 20230074159 A1)
Regarding claim 20, Wang in view of Boo, Val, Jeng, Chen2, and Kurihara discloses package of claim 19, but is silent to a first pitch of the first terminals being greater than a third pitch of the third terminals and a width of the first terminals are greater than a width of the third terminals.
Huang discloses (Fig. 5) a package (120e) wherein a pitch (154) between the interposer (160) and the chip package (120, 121, 122, 102, Fig. 1C, col. 3, lines 61-67) is larger than a pitch (192) between the interposer and a substrate (180); and the width of 154 is larger than the width of 192.
One of ordinary skill in the art at before the effective filing date of the invention would have substituted the interposer structure of Huang for the interposer structure of Wang for enhancing connectivity and reliable bonding between the chip package and the interposer.
Wang’s modified package is also silent to a first projected shape of the memory package on the second PCB is substantially the same as a second projected shape of the interposer on the second PCB.
Wang discloses dimensions of the first and second device in the side view, but is silent to the dimension of the devices in the plan view. Lin, in the same field of endeavor, discloses (Figs. 1A-B) a first device (120A, Fig. 2B) on interposer (230, 240, Fig. 2C) and a second device (125A, Fig. 2B) on substrate (110A, 290) showing the plan view of the first and second devices (120, 125 respectively, Figs. 1A-B) wherein the shape of the devices are the same. Practitioners in the art would have appreciated application of the same width to the aside devices would allow measurement uniformity, functional design, or aesthetic alignment. Such one of ordinary skill in the art before the effective filing date of the invention would have adopted the design layout of Lin to the package of Wang to achieve measurement uniformity and aesthetic alignment.
The modification of Lin to Wang’s modified package would result a first projected shape of the memory package on the second PCB is substantially the same as a second projected shape of the interposer on the second PCB.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin (US 20170077073 A1) and Pan (US 20230052821 A1) disclose a first package on its own interposer; the interposer is spaced apart from a second package and both the interposer and the second package are disposed on a substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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