Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-25 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al US 20170330882 A1 in view of Wei et al CN 114843270 A. Wang et al and Wei et al will be referenced to as Wang and Wei respectively henceforth.
Regarding Claim 16,
Wang teaches:
“A memory device comprising:
a memory cell having a storage element (Wang: capacitor 900, [0086], FIG. 30A) and an access device (Wang: conductive portion 162, gate dielectric 164, active areas 12, [0058], FIG. 29A: The gate electrode, gate dielectric, and active areas form the components of a transistor. That is, the gate and source/drain regions.), the access device including a conductive region (Wang: conductive portion 162, [0058], FIG. 29A) providing an active area (Wang: active area 12, [0059], FIG. 29A, FIG. 30A: The active area includes parts 12a, 12b, and 12c.);
a data line contact (Wang: intermediate metal layer 310c , [0071], FIG. 30A) coupled to conductive region of the access device through a conductive plug (Wang: digit line contact plug 310, [0076], FIG. 30A: 310 is in contact with intermediate metal layer 310c. 310 is electrically coupled to 162 through active region 12a.), the data line contact positioned above and contacting the conductive plug (Wang: 310c is above and in contact with 310.);
a cell contact coupled to the access device of the memory cell (Wang: cell contact plug 410, FIG. 30A: The cell contact is coupled to the access device by the electrical contact between 410 and 12b.);
a shallow trench isolation region adjacent to and contacting the data line contact (Wang: STI structure 14, [0088], FIG. 30A: STI 14 is in electrical contact and is adjacent to the data line contact 310c. 14 is in electrical contact with 310c as the electrical signal terminates at 14.), and adjacent to and contacting the conductive plug and the conductive region (Wang: STI structures 14, [0049], FIG. 30A: 14 is in physical contact with 310 at an underside of 310. 14 is also next to, or adjacent to, 310.); and
a dielectric structure contacting the data line contact and the cell contact (Wang: insulating layer 206, [0071], FIG. 30A), the dielectric structure on and contacting the shallow trench isolation region (Wang: FIG. 30A: 206 is in physical contact with 14 and is on 14.) and separating the data line contact from the cell contact (Wang: FIG. 30A: 206 is between 410 and 310.)”
Wang doesn’t substantially teach alone:
“the dielectric structure including a dielectric material that is different in composition from material of the shallow trench isolation region.”
However, Wang and Wei together teach:
“the dielectric structure including a dielectric material that is different in composition from material of the shallow trench isolation region (Wang: [0050]: 14 may be made of silicon oxide; Wei: insulating spacer 112, [0062-0063] FIG. 8A: 112 separates the bit line from the cell contact. 112 may comprise silicon nitride.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wang is modifiable in view of Wei by substituting the material of dielectric structure from silicon oxide to silicon nitride.
This is because Wang teaches a silicon oxide dielectric structure which electrically and physically isolates a bit line from an electrode. Wang doesn’t substantively teach a dielectric structure made of silicon nitride. Wei teaches a silicon oxide dielectric structure which electrically and physically isolates a bit line from an electrode. Wei further teaches a dielectric structure made of silicon nitride. Because both Wang and Wei have a dielectric structure which electrically and physically isolates a bit line from an electrode, one of ordinary skill in the art would have deemed it obvious to substitute the silicon oxide dielectric structure of Wang for a silicon nitride dielectric structure of Wei for the predictable result of a dielectric structure which electrically and physically isolates a bit line from an electrode.
Regarding Claim 17,
Wang/Wei teaches:
“The memory device of claim 16, wherein the dielectric structure is a non-oxide dielectric (Wei: insulating spacer 112, [0062-0063] FIG. 8A: 112 separates the bit line from the cell contact. 112 may comprise silicon nitride.).”
Regarding Claim 18,
Wang/Wei teaches:
“The memory device of claim 17, wherein the non-oxide dielectric includes one or more of a dielectric nitride or silicon carbide (Wei: insulating spacer 112, [0062-0063] FIG. 8A: 112 separates the bit line from the cell contact. 112 may comprise silicon nitride.).”
Regarding Claim 19,
Wang/Wei teaches:
“The memory device of claim 16, wherein the data line contact connects to a metallic data line (Wang: metal layer 610, [0075], FIG. 30A: 310c is in electric contact with 610.).”
Regarding Claim 20,
Wang/Wei teaches:
“The memory device of claim 16, wherein the access device is a transistor (Wang: conductive portion 162, gate dielectric 164, active areas 12, [0058], FIG. 29A: The gate electrode, gate dielectric, and active areas form the components of a transistor. That is, the gate and source/drain regions.) and the storage element is a capacitor (Wang: capacitor 900, [0086], FIG. 30A)”
Regarding Claim 21,
Wang/Wei teaches:
“The memory device of claim 17, wherein the non-oxide dielectric includes a dielectric nitride (Wei: insulating spacer 112, [0062-0063] FIG. 8A: 112 separates the bit line from the cell contact. 112 may comprise silicon nitride.).”
Regarding Claim 22,
Wang/Wei teaches:
“The memory device of claim 16, wherein the memory device includes an isolation dielectric vertically along and contacting the data line contact (Wang: annular spacer 520, [0069], [0072] FIG. 30A: 520 is vertically along 612. 520 may be silicon oxide. Silicon oxide is a dielectric.) and on and contacting the dielectric structure (Wang: FIG. 30A: 520 is directly on a side of 206.).”
Regarding Claim 23,
Wang/Wei teaches:
“The memory device of claim 16, wherein the conductive plug is a polysilicon plug (Wang: [0070], [0076]: 310 is made of polysilicon.).”
Regarding Claim 24,
Wang/Wei teaches:
“The memory device of claim 16, wherein the data line contact includes tungsten (Wang: [0071]: 310c may comprise tungsten.).”
Regarding Claim 25,
Wang/Wei teaches:
“The memory device of claim 19, wherein the metallic data line includes tungsten (Wang: [0073]: 610 may comprise tungsten.).”
Regarding Claim 27,
Wang/Wei teaches:
“The memory device of claim 16, wherein the active area include silicon (Wang: [0049], FIG. 30A: the semiconductor substrate 10 includes silicon. The active area 12 is part of the substrate and therefore also comprises silicon.).”
Regarding Claim 28,
Wang/Wei teaches:
“The memory device of claim 16, wherein the dielectric structure is an atomic layer deposited non-oxide dielectric (Wang/Wei: Wang: [0068]: 206 may be deposited with ALD.; Wei: [0063]: 112 may be a silicon nitride).”
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wang/Wei in view of Hwang et al US 20150126013 A1. Hwang et al will be referenced to as Hwang henceforth.
Regarding Claim 26,
Wang/Wei teaches:
“The memory device of claim 16,”
Wang/Wei doesn’t substantially teach:
“wherein the shallow trench isolation region includes a dielectric nitride”
However, Hwang teaches:
“wherein the shallow trench isolation region includes a dielectric nitride (Hwang: isolation layers 44, [0102]: 44 may comprise a liner which comprises silicon nitride.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wang/Wei is modifiable in view of Hwang by substituting the STI structure of Wang with the STI structure of Huang.
This is because Wang/Wei teaches a STI structure comprising a silicon oxide fill. Wang/Wei doesn’t substantively teach a STI structure comprising a silicon nitride liner. Hwang teaches a STI structure comprising a silicon oxide fill. Hwang further teaches a STI structure comprising a silicon nitride liner. Because both Wang/Wei and Hwang have a STI structure comprising a silicon oxide fill, one of ordinary skill in the art would have deemed it obvious to substitute the STI structure of Wang/Wei for the STI structure of Hwang for the predictable result of an STI structure which isolates active areas of neighboring semiconductor devices.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wang and Wei.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“a shallow trench isolation region in direct physical contact with both the data line contact, the conductive plug, and the conductive region”
It would overcome the current rejections for claim 16 given the replacement of relevant limitations pertaining to, “a shallow trench isolation region” in claim 16. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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