Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 16-20 without traverse in the reply filed on 11/25/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al US 20150126013 A1. Hwang et al will be referenced to as Hwang henceforth.
Regarding Claim 16,
Hwang teaches:
“A memory device comprising:
a memory cell having a storage element ([0045], [0092], FIG. 3: a capacitor may be the storage element. The capacitor includes a storage node 221.) and an access device (transistor, [0046]: The transistor is not illustrated, but is connected to the first contact plug.);
a data line contact coupled to the access device of the memory cell (first contact plug 207, [0043], [0088], FIG. 3);
a cell contact coupled to the access device of the memory cell (first plug 210, [0089], FIG. 3: 210 is part of the second contact plug);
a shallow trench isolation region adjacent to and contacting the data line contact (isolation layer 202, isolation layer 44, [0016], [0020], [0087], [0102], FIG. 3, FIG. 6D: FIG. 3 and FIG. 6D refer to the same embodiment. Therefore, 202 is the same as 44.); and
a dielectric structure contacting the data line contact and the cell contact (first spacer 215, [0095], [0097]. 215 may be made of silicon nitride. Silicon nitride is a dielectric.), the dielectric structure on and contacting the shallow trench isolation region (FIG. 3) and separating the data line contact from the cell contact (FIG. 3: 215 is between 207 and 210.). ”
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Regarding Claim 17,
Hwang teaches:
“The memory device of claim 16, wherein the dielectric structure is a non-oxide dielectric ([0097]: Silicon nitride does not include an oxide.).”
Regarding Claim 18,
Hwang teaches:
“The memory device of claim 17, wherein the non-oxide dielectric includes one or more of a dielectric nitride or silicon carbide ([0097]: Silicon nitride is a dielectric nitride.).”
Regarding Claim 19,
Hwang teaches:
“The memory device of claim 16, wherein the data line contact connects to a metallic data line (bit line 208, [0097], [0110], FIG. 3, FIG. 6D: 208 and 207 are in direct contact. The bit line may include a tungsten layer.).”
Regarding Claim 20,
Hwang teaches:
“The memory device of claim 16, wherein the access device is a transistor and the storage element is a capacitor ([0045-0046], [0092], FIG. 3: a capacitor may be the storage element. The capacitor includes a storage node 221. The transistor is not illustrated, but is connected to the first contact plug.)”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812