Prosecution Insights
Last updated: April 19, 2026
Application No. 18/234,305

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Aug 15, 2023
Examiner
SITTA, GRANT
Art Unit
2622
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
86%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
664 granted / 924 resolved
+9.9% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
32 currently pending
Career history
956
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 924 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1,11,15, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak et al (2021/0036087) hereinafter, Kwak. In regards to claim 1, Kwak teaches a display device comprising (abstract): A display apparatus includes: a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape; a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits; a first voltage line extending on the display area in the first direction; a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line; a test circuit outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other. a first display area including a plurality of data lines extending in a first direction (fig. 5a data lines extending down in the center)(fig. 1 DL);Examiner notes the “display area” is merely a label. PNG media_image1.png 642 602 media_image1.png Greyscale a second display area at one side of the first display area, comprising a plurality of data lines shorter than the data lines of the first display area (fig. 5a area to the left data lines are shorter than center section, see annotated drawing below); a first non-display area adjacent to the first display area (fig. 2 non-display area below center area); and PNG media_image2.png 736 610 media_image2.png Greyscale a second non-display area adjacent to the second display area, comprising a plurality of load matching units respectively connected to the plurality of data lines of the second display area and configured to compensate for load capacitance of the plurality of data lines of the second display area (fig. 5b CML in second non-display area).[138-139] [0139] The load matching portion CLM may include one or more load compensation capacitors Clm, for example. As described above, each column of a circuit group PUCL may include three pixel circuit columns PCCLs. In this case, as shown in an enlarged portion view of FIG. 5B, the load matching portion CLM includes three load compensation capacitors Clm, each of the load compensation capacitors Clm corresponding to one of the pixel circuit columns PCCL of a corresponding column of the circuit group PUCL. The load compensation capacitors Clm may compensate for the load difference described above corresponding to each pixel circuit column PCCL. In regards to claim 15, Kwak teaches a display device comprising (abstract): a first display area including a plurality of data lines extending in a first direction (fig. 1 DL) first direction); a second display area at one side of the first display area, comprising a plurality of data lines extending in the first direction, the second display area having a width smaller than a width of the first display area in the first direction; and (fig. 5a and 5b DA2 annotated below. Examiner note currently the “second display area” is merely a label). a non-display area surrounding the first and second display areas (fig. 5b non-display surrounding display area), PNG media_image3.png 720 560 media_image3.png Greyscale wherein the non-display area comprises a plurality of load matching units including a plurality of compensation capacitors respectively connected to the plurality of data lines of the second display area. (fig. 5b CML in second non-display area).[138-139] In regards to claim 18, Kwak teaches display device comprising (abstract): a first display area including a plurality of data lines extending in a first direction (fig. 5a data lines extending down in the center)(fig. 1 DL) and fig. 5b center display area); a second display area at one side of the first display area, comprising a plurality of data lines shorter than the data lines of the first display area; (fig. 5b (DA2)) a first non-display area adjacent to the first display area, comprising a first circuit part; (fig. 5b area above DA1) a second non-display area adjacent to the second display area, comprising a second circuit part and a plurality of load matching units between the second circuit part and the second display area and connected to each of the plurality of data lines of the second display area;(fig. 5b non-display area above DA2)[130-138] and a third non-display area adjacent to the second display area and the second non-display area, comprising a third circuit part(fig. 5b non-display area to left of DA2 containing CLM)). PNG media_image4.png 690 590 media_image4.png Greyscale In regards to claim 11, Kwak teaches the display device of claim 1, further comprising a third non-display area adjacent to the second display area and the second non-display area, and including a third circuit part (fig. 5a and 5b right side of display and corresponding circuits))). In regards to claim 17, Kwak teaches the display device of claim 15, wherein the second display area further comprises a driving voltage line extending in parallel with the data lines (fig. 8 DL and PL), and each of the plurality of compensation capacitors includes: a first capacitor electrode electrically connected to the data line; and a second capacitor electrode electrically connected to the driving voltage line [162-167,173-180] (fig. 8 CLM, DL and LPL) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Chiu et al (2005/0140642) hereinafter, Chiu. In regards to claim 2, Kwak teaches the display device of claim 1, wherein the second display area comprises a plurality of data lines having lengths different from each other (fig. 5b data lines have different length along the curve of the circumference of the circle)[138] Kwak, and Kwak fails to teach the second non-display area comprises a plurality of load matching units having different lengths corresponding to the lengths of the data lines of the second display area. However, Chiu teaches teach the second non-display area comprises a plurality of load matching units having different lengths corresponding to the lengths of the data lines of the second display area.[0036-0037] [0037] In another aspect of the present invention, the RC characteristic of adjacent data input lines can be matched by providing dummy conductor lines to the data input lines. The dummy conductor lines may be of different physical characteristics (e.g., length, width and/or thickness, or material) for different data input lines to match the RC characteristic of the data input lines. In one embodiment, the length of the dummy conductor line for each data input line is chosen to extend the data input lines to be at least as long the longest data input line. In another embodiment, the length of the dummy conductor line for each data input line is chosen to extend the data input lines to different lengths in order to match the RC characteristics in the data input lines. It is within the scope and spirit of the present invention that other physical characteristic of the dummy conductor lines may be adopted in the alternative or in addition to the length (e.g. the width, thickness and/or material) of the dummy conductor line can also be controlled to effect matching the RC characteristics of the data input lines. It would have been obvious to one of ordinary skill in the art to modify the teachings of Kwak to further include the second non-display area comprises a plurality of load matching units having different lengths corresponding to the lengths of the data lines of the second display area as taught by Chiu in order to reduce disparity in image qualities [0036]. In regards to claim 3, Kwak in view of Chiu teaches the display device of claim 2, wherein, as a length of a data line from among the data lines becomes short, a length of the load matching unit is increased, and as the length of the load matching unit is increased, a load capacitance of the load matching unit is increased.[0036-0037] at least length Chiu In regards to claim 16, Kwak in view of Chiu, see rational of claim 2, teaches the display device of claim 15, wherein the second display area comprises a plurality of data lines having lengths different from each other, (fig. 5b data lines have different length along the curve of the circumference of the circle)[138] Kwak and each of the plurality of load matching units includes a number of the compensation capacitors, which is different depending on the lengths of the data lines of the second display area [139-141] Kwak in view of [0036-0037] Chiu. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Bae et al (2019/0181211) hereinafter, Bae In regards to claim 7, Kwak teaches the display device of claim 1, wherein the first non-display area comprises: a pad portion (fig. 2 pad); Kwak fails to expressly show a plurality of first fan-out lines connected to the pad portion; However, Bae teaches a plurality of first fan-out lines connected to the pad portion (fig. 4 (pad and fan out). It would have been obvious to one of ordinary skill in the art to modify the teachings of Kwak to further include a plurality of first fan-out lines connected to the pad portion as taught by Bae in order to provide signals to the display and address a display. Therefore, Kwak in view of Bae teaches and a first circuit part ((fig. 7 demux circuit) Bae) connected between the plurality of first fan-out lines and the plurality of data lines (fig. 7 DA and fanout) Bae), and the second non-display area comprises: a plurality of second fan-out lines connected to the pad portion (fig. 6 (fanout for second))Kwak; a second circuit part connected to the plurality of second fan-out lines (fig. 6 fanout); and a plurality of lead lines connected between the second circuit part and the second display area.(fig. 6 leads from 210 and 170s) Kwak and fig. 7 (demux) Bae. In regards to claim 8, Kwak in view of Bae teaches the display device of claim 7, wherein the second circuit part comprises: a demultiplexer configured to output a data voltage received from one of the plurality of second fan-out lines to the plurality of lead lines(fig. 6 leads from 210 and 170s) Kwak and fig. 7 (demux) Bae; and a scan driver configured to generate a scan signal based on a scan control signal received from the pad portion (fig. 1 (120) scan driver) Kwak. 4. Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Jung et al 2019/0096978 hereinafter, Jung. In regards to claim 12, Kwak teaches the display device of claim 11, wherein the third circuit part comprises: a scan driver configured to generate a scan signal based on a scan control signal (fig. 1 130 scan driver across from 120).; and Kwak an antistatic circuit configured to remove static electricity flowing from the outside. However, Jung teaches an antistatic circuit configured to remove static electricity flowing from the outside. (fig. 9 (510-530) Jung). It would have been obvious to one of ordinary skill in the art to modify the teachings of Kwak to include an antistatic circuit configured to remove static electricity flowing from the outside as taught by Jung in order to remove static and help prevent damage. In regards to claim 13, Kwak in view of Jung teaches, see rational of claim 12, the display device of claim 11, wherein the third circuit part comprises: a plurality of scan drivers configured to generate a scan signal based on a scan control signal (fig. 1 130 and fig. 18 103ss)) Kwak; an antistatic circuit configured to remove static electricity flowing from the outside (fig. 9 (510-530) Jung); and a plurality of load matching units connected to the plurality of data lines of the second display area.(fig. 5b CLMS)) Kwak In regards to claim 14, Kwak in view of Jung teaches the display device of claim 13, wherein the plurality of load matching units are between the plurality of scan drivers (fig. 6 clms between 120s on bottom and 120s on top) Kwak. Allowable Subject Matter Claims 4-6, 9-10, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-6084. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRANT SITTA/Primary Examiner, Art Unit 2622
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Prosecution Timeline

Aug 15, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
86%
With Interview (+13.9%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 924 resolved cases by this examiner. Grant probability derived from career allow rate.

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