DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 20 in the Applicant’s response dated 3 June 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendments to claim 11 in the Applicant’s response dated 3 June 2026 in lieu of the 35 U.S.C. 112(b) rejection presented in the previous office action. The 35 U.S.C. 112(b) rejection to claims 11 and 12 have therefore been withdrawn.
The Examiner acknowledges the addition of new claims 21-26 in the Applicant’s response dated 3 June 2026. The new claims have been addressed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 and 20-26 are rejected under 35 U.S.C. 103 as being unpatentable over Marc Huesgen et al. (US 2022/0285286 A1; hereinafter “Huesgen”) in view of Eungkyu Kim et al. (US 2022/0262699 A1; hereinafter “Kim”).
Regarding Claim 1, Huesgen teaches a chip packaging structure, comprising:
a substrate (202, Fig. 3, para [0027] describes a substrate 202), comprising:
a signal transmitting wiring structure embedded in the substrate (ST, annotated Fig. 3, para [0028] describes a plurality of interconnects 221 in the substrate 202 wherein para [0101] describes wherein an interconnect may be configured to provide an electrical path for a signal as depicted by signal transmitting wiring structure ST of annotated Fig. 3 connected to integrated circuits), and
a thermal transmitting wiring structure embedded in the substrate (TT, annotated Fig. 3, para [0028] describes a plurality of interconnects 221 in the substrate 202 wherein para [0036] describes wherein an interconnect may be configured to dissipate heat as depicted by thermal transmitting wiring structure TT of annotated Fig. 3 connected to a through via);
a first chip on the substrate and electrically connected with the signal transmitting wiring structure (204, Fig. 3, para [0027] describes an integrated device 204 on the substrate 202 wherein first chip 204 is electrically connected to signal transmitting wiring structure ST of annotated Fig. 3); and
at least one thermal conductive structure on the substrate (211, Fig. 3, para [0031] describes a plurality of through mold vias 211 configured to help dissipate heat wherein the plurality of through mold vias comprise a thermal conductive structure), in thermal contact with the thermal transmitting wiring structure (211 and TT, annotated Fig. 3, para [0030] describes wherein the thermal conductive structure 211 is coupled to interconnects 211 specifically a thermal transmitting wiring structure TT of the interconnects 211 as shown in annotated Fig. 3), and laterally surrounding the first chip (Fig. 3 and Fig. 11 depict wherein thermal conductive structures 211 laterally surround the first chip 204).
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Huesgen fails to explicitly disclose wherein the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction.
However, Kim teaches a similar chip packaging structure wherein the thermal transmitting wiring structure (34 and TWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a heat transfer wiring 34 comprising a thermal wiring structure TWS2) is located between the first chip (61, annotated Fig. 3, para [0013] describes a first active chip 61) and the signal transmitting wiring structure in a vertical direction (33, VD and SWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a signal transfer wiring 33 comprising a signal wiring structure SWS2 wherein the thermal wiring structure TWS2 is located between the first chip 61 and at least a rightmost portion of the signal transmitting wiring structure SWS2 in a vertical direction VD).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huesgen with Kim to further disclose a chip packaging structure wherein the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction in order to provide the well-known advantage of providing a thermal wiring structure closest to a semiconductor chip and a passive chip coupled to a heat spreader in order to provide the shortest possible connection between the semiconductor chip and passive chip resulting in faster thermal dissipation and a decrease in the amount of thermal wiring needed therefore lowering the manufacturing cost of the thermal wiring structure in a chip packaging structure and to further provide the advantage of physically spacing apart a heat transfer wiring and a signal wiring structure in order to prevent the possible degradation of the signal wiring structure (Kim, para [0015]).
Regarding Claim 2, the combination of Huesgen and Kim teaches the chip packaging structure of claim 1, further comprising:
a mold compound layer on the substrate and covering the first chip (Huesgen, 209, Fig. 3, para [0032] describes an encapsulating layer 209 comprised of a mold material at least partially covering the first chip 204 on the substrate 202), wherein the at least one thermal conductive structure is embedded in the mold compound layer (Huesgen, 211, Fig. 3, para [0032] describes wherein mold compound layer 209 may encapsulate at least one thermal conductive structure 211); and
a thermal conductive cover on the mold compound layer and in thermal contact with the at least one thermal conductive structure (Huesgen, 211, Fig. 3, para [0033] describes a metal layer 210 covering a top surface of the mold compound layer 209 and coupled to thermal conductive structures 211).
Regarding Claim 3, the combination of Huesgen and Kim teaches the chip packaging structure of claim 1, further comprising:
a ball grid array on a side of substrate opposite to the first chip and the at least one thermal conductive structure (Huesgen, 230, Fig. 3, para [0028] describes a plurality of solder interconnects 230 which may form a ball grid array on a bottom portion of the substrate 202), the ball grid array comprising:
a plurality of signal solder balls in contact with the signal transmitting wiring structure (Huesgen, SSB, annotated Fig. 3 II and Fig. 14C, para [0028] describes wherein a plurality of the solder interconnects of the ball grid array 230 may be coupled to the plurality of interconnects 221 wherein solder balls SSB coupled to signal transmitting wiring structure ST of annotated Fig. 3 comprise a plurality of signal solder balls further wherein Fig. 14C depicts the layered contact structure of interconnects 221), and
at least one thermal solder ball in contact with the thermal transmitting wiring structure (Huesgen, TSB, annotated Fig. 3 II depicts wherein at least one thermal solder ball TSB is in contact with the thermal wiring structure TT).
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Regarding Claim 4, the combination of Huesgen and Kim teaches the chip packaging structure of claim 2, wherein the at least one thermal conductive structure comprises:
a plurality of thermal conductive blocks each vertically penetrating through the mold compound layer and comprising a top surface in contact with the thermal conductive cover and a bottom surface in contact with a thermal pad connected with the thermal transmitting wiring structure (Huesgen, 211, Fig. 3, para [0031] describes a plurality of through mold vias 211 of a thermal conductive structure wherein each through mold via comprises a thermal conductive block vertically penetrating through the mold compound layer 209 and comprising a top surface in contact with thermal conductive cover 210 and a bottom surface in contact with a thermal pad TP from annotated Fig. 3 II connected to the thermal transmitting wiring structure TT from annotated Fig. 3).
Regarding Claim 5, the combination of Huesgen and Kim discloses all the limitations of claim 4.
Huesgen and Kim fail to explicitly disclose the chip packaging structure of claim 4, wherein: a ratio between a first lateral area of each thermal conductive block and a second lateral area of the first chip is in a range between about 1/20 and about 1/10.
However, Huesgen teaches a chip packaging structure, wherein a thermal conductive block may have a size, shape, spacing, and number of blocks that varies with different implementations of the chip packaging structure (211, Fig. 11, para [0055]). The disclosure of Huesgen further displays in Fig. 11 wherein a width of a first chip (204, Fig. 11) is approximately three to five thermal conductive blocks wide in both a first direction and a perpendicular second direction (211, Fig. 11) wherein a resulting lateral area of a first chip may be approximately 9 to 25 times greater than a lateral area of a thermal conductive block.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different widths and sizes of thermal conductive blocks resulting in a ratio between a first lateral area of each thermal conductive block and a second lateral area of a first chip in a range between about 1 to 20 and about 1 to 10 in order to provide the advantage of reducing the number of thermal conductive blocks needed to a minimum amount in order to provide adequate thermal dissipation while also providing effective EMI shielding (Huesgen, para [0055]) see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B).
Regarding Claim 6, the combination of Huesgen and Kim teaches the chip packaging structure of claim 1, further comprising:
a second chip on the substrate and outside the at least one thermal conductive structure (Huesgen, 206, Fig. 3, para [0027] describes a second integrated circuit device 206 which can be seen located outside of the thermal conductive structure comprised of through vias 211 in Fig. 3).
Regarding Claim 7, the combination of Huesgen and Kim discloses all the limitations of claim 6.
Huesgen and Kim fail to explicitly disclose the chip packaging structure of claim 6, wherein: a first operating power of the first chip is greater than a second operating power of the second chip.
However, Huesgen teaches a chip packaging structure, wherein a first chip may comprise a processor, power amplifier, a system on a chip, or an integrated circuit die which may be configured to perform logic operations (204, Fig. 3, para [0037] and para [0038]) and a second chip may comprise a memory chip or a sensing device such as a MEMS or NEMS device (206, Fig. 3, para [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention try different devices for a first chip and a second chip resulting in a first chip which has a greater operating power than a second chip in order to provide the advantage of enabling multiple different device configurations in one chip packaging structure which may provide a first chip to be used in combination with a second chip in a chip packaging structure (Huesgen, para [0037] and para [0038]), further providing the well-known advantage of simplifying the manufacturing process and diversifying the applications to which a chip packaging structure may be used.
Regarding Claim 8, the combination of Huesgen and Kim teaches the chip packaging structure of claim 6, wherein:
the first chip comprises at least one of a micro processing chip, a logic control chip, a power management chip, a driver chip, and an analog chip (Huesgen, 204, Fig. 3, para [0037] and para [0038] describes wherein a first chip 204 may comprise a processor, power amplifier, a system on a chip, or an integrated circuit die which may be configured to perform logic operations such as in a logic control chip); and
the second chip comprises at least one of a memory chip and a sensing chip (Huesgen, 206, Fig. 3, para [0037] states wherein integrated device 206 may be a memory integrated device or a sensing chip such as a MEMS or NEMS device).
Regarding Claim 9, the combination of Huesgen and Kim teaches the chip packaging structure of claim 1, further comprising:
a third chip on the substrate and beside the first chip, and being laterally surrounded by the at least one thermal conductive structure (Huesgen, 208, Fig. 3, para [0027] describes a third integrated device 208 comprising a third chip on the substrate 202 beside the first chip 204 and laterally surrounded on at least one side by thermal conductive structure comprised of through vias 211).
Regarding Claim 10, the combination of Huesgen and Kim teaches the chip packaging structure of claim 9, wherein:
a portion of the at least one thermal conductive structure is located between the third chip and the first chip (Huesgen, 211, Fig. 3 depicts wherein at least a portion of the at least one thermal conductive structure is located between the third chip 208 and first chip 204 as depicted by through via 211 between first chip 204 and third chip 208).
Regarding Claim 11, the combination of Huesgen and Kim discloses all the limitations of claim 1.
Huesgen discloses wherein the at least one thermal conductive structure is configured to help dissipate heat (Huesgen, 211, Fig. 3, para [0031] describes wherein the at least one thermal conductive structure 211 is configured to help dissipate heat).
Huesgen fails to explicitly disclose the chip packaging structure of claim 1, wherein: a material of the at least one thermal conductive structure has a thermal conductive coefficient greater than 1 W/(m·K).
However, Kim teaches a similar chip packaging structure, wherein:
a material of the at least one thermal conductive structure has a thermal conductive coefficient greater than 1 W/(m·K) (75, annotated Fig. 3, para [0014] and para [0033] describes through electrodes 75 on a substrate 30 wherein the thermal conductive structures 75 comprise one or more materials exhibiting excellent thermal conductivity such as copper wherein it is well-known in the art that copper has a thermal conductive coefficient greater than 1 W/(m·K)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huesgen and Kim to further disclose a chip packaging structure wherein a material of a thermal conductive structure has a conductive coefficient greater than 1 in order to provide the well-known advantage of providing a thermal conductive structure comprised of a metal which may dissipate heat from an integrated circuit chip efficiently and effectively preventing overheating and undesirable effects in the chip.
Regarding Claim 12, the combination of Huesgen and Kim teach the chip packaging structure of claim 11, wherein:
the material is one of a metal, a ceramic material, or a silicon material (Kim, 75, Fig. 3, para [0033] describes wherein a material of the at least one thermal conductive structure 75 may be a metal material such as copper).
Regarding Claim 13, the combination of Huesgen and Kim discloses all the limitations of claim 1.
Huesgen fails to explicitly disclose wherein: a ratio between a first wiring width of the thermal transmitting wiring structure and a second wiring width of the signal transmitting wiring structure is in a range between about 1.5 to about 2.
However, Kim teaches a similar chip packaging structure in the disclosure of their invention, wherein a portion of a thermal transmitting wiring structure (34, Fig. 3) and a portion of a signal transmitting wiring structure (33, Fig. 3) may be characterized by a width that decreases as the wiring vertically descends. The disclosure displays in Fig. 3 wherein said width of a thermal transmitting wiring structure and signal transmitting wiring structure at a top portion appears to be 1.5 to about 2 times the size of a width of the decreasing section vertically descending into the wiring substrate. The disclosure further displays in Fig. 3 thermal transmitting wiring structures and signal transmitting wiring structures of varying widths throughout the wiring structure of the invention.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Huesgen and Kim to try different widths of thermal transmitting wiring structures and signal transmitting wiring structures while reducing the width of a thermal transmitting wiring structure, resulting in a ratio of a first wiring width of a thermal transmitting wiring structure to a second wiring width of a signal transmitting wiring structure in order to provide the advantage of providing landing pads for via plugs of a wiring layer which enable an electrical and thermal connection reducing the risk of current and thermal leakage into surrounding layers and further reducing the size of a thermal wiring structure to provide the advantage of providing separation between thermal transfer wiring and signal wiring and enabling additional electrical components to be embedded into a wiring layer, such as a semiconductor chip (Kim, para [0014] and para [0015]) see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B).
Regarding Claim 20, Huesgen teaches a semiconductor structure, comprising:
a chip packaging structure (300, Fig. 3, para [0039] describes an integrated circuit package 300), comprising:
a substrate (202, Fig. 3, para [0027] describes a substrate 202), comprising:
a signal transmitting wiring structure embedded in the substrate (ST, annotated Fig. 3, para [0028] describes a plurality of interconnects 221 in the substrate 202 wherein para [0101] describes wherein an interconnect may be configured to provide an electrical path for a signal as depicted by signal transmitting wiring structure ST of annotated Fig. 3 connected to integrated circuits), and
a thermal transmitting wiring structure embedded in the substrate (TT, annotated Fig. 3, para [0028] describes a plurality of interconnects 221 in the substrate 202 wherein para [0036] describes wherein an interconnect may be configured to dissipate heat as depicted by thermal transmitting wiring structure TT of annotated Fig. 3 connected to a through via);
a first chip on the substrate and electrically connected with the signal transmitting wiring structure (204, Fig. 3, para [0027] describes an integrated device 204 on the substrate 202 wherein first chip 204 is electrically connected to signal transmitting wiring structure ST of annotated Fig. 3); and
at least one thermal conductive structure on the substrate (211, Fig. 3, para [0031] describes a plurality of through mold vias 211 configured to help dissipate heat wherein the plurality of through mold vias comprise a thermal conductive structure), in thermal contact with the thermal transmitting wiring structure (211 and TT, annotated Fig. 3, para [0030] describes wherein the thermal conductive structure 211 is coupled to interconnects 211 specifically a thermal transmitting wiring structure TT of the interconnects 211 as shown in annotated Fig. 3), and laterally surrounding the first chip (Fig. 3 and Fig. 11 depict wherein thermal conductive structures 211 laterally surround the first chip 204); and
a ball grid array (230, Fig. 3, para [0028] describes a plurality of solder interconnects 230 which may form a ball grid array on a bottom portion of the substrate 202), comprising:
a plurality of signal solder balls in contact with the signal transmitting wiring structure (SSB, annotated Fig. 3 II and Fig. 14C, para [0028] describes wherein a plurality of the solder interconnects of the ball grid array 230 may be coupled to the plurality of interconnects 221 wherein solder balls SSB coupled to signal transmitting wiring structure ST of annotated Fig. 3 comprise a plurality of signal solder balls further wherein Fig. 14C depicts the layered contact structure of interconnects 221), and
at least one thermal solder ball in contact with the thermal transmitting wiring structure (TSB, annotated Fig. 3 II depicts wherein at least one thermal solder ball TSB is in contact with the thermal wiring structure TT).
Huesgen fails to explicitly disclose wherein the semiconductor structure comprises a printed circuit board; a ball grid array connected between the printed circuit board and the chip packaging structure; and wherein the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction.
However, Kim teaches a similar semiconductor structure, comprising a printed circuit board (30, Fig. 3, para [0014] describes wherein wiring structure 30 may include a printed circuit board); and a ball grid array connected between the printed circuit board and the chip packaging structure (41 and 42, Fig. 3, para [0020] describes solder balls 41 and 42 forming a ball grid array between a printed circuit board in the wiring structure 30 and a chip packaging structure 61 and 71); and
wherein the thermal transmitting wiring structure (34 and TWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a heat transfer wiring 34 comprising a thermal wiring structure TWS2) is located between the first chip (61, annotated Fig. 3, para [0013] describes a first active chip 61) and the signal transmitting wiring structure in a vertical direction (33, VD and SWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a signal transfer wiring 33 comprising a signal wiring structure SWS2 wherein the thermal wiring structure TWS2 is located between the first chip 61 and at least a rightmost portion of the signal transmitting wiring structure SWS2 in a vertical direction VD).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huesgen with Kim to further disclose a semiconductor structure comprising a printed circuit board and a ball grid array comprised between a printed circuit board and a chip packaging structure in order to provide the well-known advantage of enabling a chip packaging structure to be coupled to a printed circuit board providing external connections enabling communication between device components and power to be transmitted to a chip so that it may function as intended and to further disclose wherein the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction in order to provide the well-known advantage of providing a thermal wiring structure closest to a semiconductor chip and a passive chip coupled to a heat spreader in order to provide the shortest possible connection between the semiconductor chip and passive chip resulting in faster thermal dissipation and a decrease in the amount of thermal wiring needed therefore lowering the manufacturing cost of the thermal wiring structure in a chip packaging structure and to further provide the advantage of physically spacing apart a heat transfer wiring and a signal wiring structure in order to prevent the possible degradation of the signal wiring structure (Kim, para [0015]).
Regarding Claim 21, the combination of Huesgen and Kim teaches the semiconductor structure of claim 20, further comprising:
a mold compound layer on the substrate and covering the first chip (Huesgen, 209, Fig. 3, para [0032] describes an encapsulating layer 209 comprised of a mold material at least partially covering the first chip 204 on the substrate 202), wherein the at least one thermal conductive structure is embedded in the mold compound layer (Huesgen, 211, Fig. 3, para [0032] describes wherein mold compound layer 209 may encapsulate at least one thermal conductive structure 211); and
a thermal conductive cover on the mold compound layer and in thermal contact with the at least one thermal conductive structure (Huesgen, 211, Fig. 3, para [0033] describes a metal layer 210 covering a top surface of the mold compound layer 209 and coupled to thermal conductive structures 211).
Regarding Claim 22, the combination of Huesgen and Kim teaches the semiconductor structure of claim 20, further comprising:
a ball grid array on a side of substrate opposite to the first chip and the at least one thermal conductive structure (Huesgen, 230, Fig. 3, para [0028] describes a plurality of solder interconnects 230 which may form a ball grid array on a bottom portion of the substrate 202), the ball grid array comprising:
a plurality of signal solder balls in contact with the signal transmitting wiring structure (Huesgen, SSB, annotated Fig. 3 II and Fig. 14C, para [0028] describes wherein a plurality of the solder interconnects of the ball grid array 230 may be coupled to the plurality of interconnects 221 wherein solder balls SSB coupled to signal transmitting wiring structure ST of annotated Fig. 3 comprise a plurality of signal solder balls further wherein Fig. 14C depicts the layered contact structure of interconnects 221), and
at least one thermal solder ball in contact with the thermal transmitting wiring structure (Huesgen, TSB, annotated Fig. 3 II depicts wherein at least one thermal solder ball TSB is in contact with the thermal wiring structure TT).
Regarding Claim 23, the combination of Huesgen and Kim teaches the semiconductor structure of claim 21, wherein the at least one thermal conductive structure comprises:
a plurality of thermal conductive blocks each vertically penetrating through the mold compound layer and comprising a top surface in contact with the thermal conductive cover and a bottom surface in contact with a thermal pad connected with the thermal transmitting wiring structure (Huesgen, 211, Fig. 3, para [0031] describes a plurality of through mold vias 211 of a thermal conductive structure wherein each through mold via comprises a thermal conductive block vertically penetrating through the mold compound layer 209 and comprising a top surface in contact with thermal conductive cover 210 and a bottom surface in contact with a thermal pad TP from annotated Fig. 3 II connected to the thermal transmitting wiring structure TT from annotated Fig. 3).
Regarding Claim 24, the combination of Huesgen and Kim teaches the semiconductor structure of claim 20, further comprising:
a second chip on the substrate and outside the at least one thermal conductive structure (Huesgen, 206, Fig. 3, para [0027] describes a second integrated circuit device 206 which can be seen located outside of the thermal conductive structure comprised of through vias 211 in Fig. 3).
Huesgen and Kim fail to explicitly disclose the chip packaging structure of claim 20, wherein a first operating power of the first chip is greater than a second operating power of the second chip.
However, Huesgen teaches a semiconductor structure wherein a first chip may comprise a processor, power amplifier, a system on a chip, or an integrated circuit die which may be configured to perform logic operations (204, Fig. 3, para [0037] and para [0038]) and a second chip may comprise a memory chip or a sensing device such as a MEMS or NEMS device (206, Fig. 3, para [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention try different devices for a first chip and a second chip resulting in a first chip which has a greater operating power than a second chip in order to provide the advantage of enabling multiple different device configurations in one semiconductor structure which may provide a first chip to be used in combination with a second chip in a chip packaging structure (Huesgen, para [0037] and para [0038]), further providing the well-known advantage of simplifying the manufacturing process and diversifying the applications to which a chip packaging structure may be used.
Regarding Claim 25, the combination of Huesgen and Kim teaches the semiconductor structure of claim 20, further comprising:
a third chip on the substrate and beside the first chip, and being laterally surrounded by the at least one thermal conductive structure (Huesgen, 208, Fig. 3, para [0027] describes a third integrated device 208 comprising a third chip on the substrate 202 beside the first chip 204 and laterally surrounded on at least one side by thermal conductive structure comprised of through vias 211),
wherein a portion of the at least one thermal conductive structure is located between the third chip and the first chip (Huesgen, 211, Fig. 3 depicts wherein at least a portion of the at least one thermal conductive structure is located between the third chip 208 and first chip 204 as depicted by through via 211 between first chip 204 and third chip 208).
Regarding Claim 26, the combination of Huesgen and Kim discloses all the limitations of claim 20.
Huesgen fails to explicitly disclose wherein: a ratio between a first wiring width of the thermal transmitting wiring structure and a second wiring width of the signal transmitting wiring structure is in a range between about 1.5 to about 2.
However, Kim teaches a similar chip packaging structure in the disclosure of their invention, wherein a portion of a thermal transmitting wiring structure (34, Fig. 3) and a portion of a signal transmitting wiring structure (33, Fig. 3) may be characterized by a width that decreases as the wiring vertically descends. The disclosure displays in Fig. 3 wherein said width of a thermal transmitting wiring structure and signal transmitting wiring structure at a top portion appears to be 1.5 to about 2 times the size of a width of the decreasing section vertically descending into the wiring substrate. The disclosure further displays in Fig. 3 thermal transmitting wiring structures and signal transmitting wiring structures of varying widths throughout the wiring structure of the invention.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Huesgen and Kim to try different widths of thermal transmitting wiring structures and signal transmitting wiring structures while reducing the width of a thermal transmitting wiring structure, resulting in a ratio of a first wiring width of a thermal transmitting wiring structure to a second wiring width of a signal transmitting wiring structure in order to provide the advantage of providing landing pads for via plugs of a wiring layer which enable an electrical and thermal connection reducing the risk of current and thermal leakage into surrounding layers and further reducing the size of a thermal wiring structure to provide the advantage of providing separation between thermal transfer wiring and signal wiring and enabling additional electrical components to be embedded into a wiring layer, such as a semiconductor chip (Kim, para [0014] and para [0015]) see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B).
Response to Arguments
Applicant's arguments filed 3 June 2026 have been fully considered but they are not persuasive.
The Applicant argues on page 8, lines 3-18 and page 9, lines 1-4 of the Applicant’s remarks that, the cited references, Huesgen, Sung and Kim, either alone or in combination, fail to disclose the following distinguishing features: “the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction.” as introduced in amended independent claims 1 and 20.
The Examiner respectfully disagrees. With respect to the Applicant’s argument that the cited references, Huesgen, Sung and Kim, either alone or in combination, fail to disclose the following distinguishing features: “the thermal transmitting wiring structure is located between the first chip and the signal transmitting wiring structure in a vertical direction.” as introduced in amended independent claims 1 and 20, this argument is not found persuasive. As indicated above, the prior art of record, Kim, discloses wherein a thermal transmitting wiring structure (34 and TWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a heat transfer wiring 34 comprising a thermal wiring structure TWS2) is located between a first chip (61, annotated Fig. 3, para [0013] describes a first active chip 61) and a signal transmitting wiring structure in a vertical direction (33, VD and SWS2, annotated Fig. 3, para [0014] describes a wiring structure 30 comprising a signal transfer wiring 33 comprising a signal wiring structure SWS2 wherein the thermal wiring structure TWS2 is located between the first chip 61 and at least a rightmost portion of the signal transmitting wiring structure SWS2 in a vertical direction VD). Therefore, the amendments to claims 1 and 20 are not found to patentably distinguish the Applicant’s claimed device from the device taught by the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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