DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of 1-19 in the reply filed on 12/15/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/15/25.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 8/16/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, and 13-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (Ayel et al. (US PGPUB 2022/0093807, hereinafter referred to as “Ayel”).
Ayel disclose the semiconductor device as claimed. See figures 1-21, with emphasis of figures 8, 10 and 17-21, and corresponding text where, Ayel teaches, in claim 1, a structure comprising:
a semiconductor substrate (101) including a trench (), the trench surrounding a portion of the semiconductor substrate (101), and the trench having a sidewall; (figure 8; [0072-0073])
a deep trench isolation region including a dielectric layer (122) and a semiconductor layer (101) (portion inside and on opposite sides of the dielectric layer (122) inside the trench ([0051], the semiconductor material is a single-crystal silicon layer), the dielectric layer (122) between the sidewall of the trench and the semiconductor layer (101) (figures 8 and 10; [0077]); and
a first active device (105) including a doped region in the semiconductor layer. (figures 8 and 10; [0072-0075])
Ayel teaches, in claim 2, further comprising:
a single-photon avalanche diode including a terminal in the portion of the semiconductor substrate (figure 8; [0073]).
Ayel teaches, in claim 3, further comprising:
a metal feature configured to connect the doped region of the first active device to the terminal of the single-photon avalanche diode (figure 8; [0072-0073]).
Ayel teaches, in claim 4, wherein the first active device is a field-effect transistor, and the doped region is a source/drain region of the field-effect transistor (figures 18 and 20; [0087-0089]).
Ayel teaches, in claim 5, wherein the field-effect transistor includes a gate on the semiconductor layer. (figures 18 and 20; [0087-0089])
Ayel teaches, in claim 6, wherein the first active device is a field-effect transistor, the doped region is a source/drain region of the field-effect transistor, and the field-effect transistor includes a gate on the semiconductor layer (figures 18 and 120; [0087-0089]).
Ayel teaches, in claim 7, wherein the semiconductor layer comprises single-crystal silicon ([0051]).
Ayel teaches, in claim 9, wherein the semiconductor layer comprises polycrystalline silicon (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 10, wherein the dielectric layer of the deep trench isolation region fully surrounds the portion of the semiconductor substrate (figure 10; [0074-0075]).
Ayel teaches, in claim 11, wherein the trench includes a bottom, and the semiconductor layer is in direct contact with the semiconductor substrate at the bottom of the trench (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 13, wherein the sidewall of the trench fully surrounds the portion of the semiconductor substrate (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 14, wherein the semiconductor substrate has a top surface, the semiconductor layer has a top surface that is coplanar with the top surface of the semiconductor substrate, and the doped region of the first active device is disposed adjacent to the top surface of the semiconductor layer (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 15, wherein the doped region of the first active device is coextensive with the top surface of the semiconductor layer (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 16, wherein the doped region of the first active device extends from the top surface of the semiconductor layer to a first depth in the semiconductor substrate, and the trench extends from the top surface of the semiconductor substrate to a second depth that is greater than the first depth (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 17, wherein the trench has a closed shape (figure 10; [0075]).
Ayel teaches, in claim 18, further comprising:
a second active device including a doped region in the semiconductor layer (figures 8 and 10; [0072-0073]).
Ayel teaches, in claim 19, wherein the first active device is a first field-effect transistor, and the second active device is a second field-effect transistor (figures 18 and 20; [0087-0089]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over (Ayel et al. (US PGPUB 2022/0093807, hereinafter referred to as “Ayel”) as applied to claim 1 above, and further in view of Yang et al. (US PGPub 2017/0186798, hereinafter referred to as “Yang”).
Ayel discloses the semiconductor device substantially as claimed. See the rejection above.
However, Ayel fails to show, in claim 8, wherein the semiconductor layer comprises amorphous silicon.
Yang provides a teaching that the semiconductor substrate can be a polysilicon or an amorphous silicon. ([0037]). In addition, Yang provides the advantages of arranging the plurality of SPAD cells more compactly, thus improving the fill factor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the semiconductor layer comprises amorphous silicon, in the device of Ayel, according to the teachings of Yang, with the motivation of arranging the plurality of SPAD cells more compactly, especially since both Ayel and Yang teach forming SPAD devices within a semiconductor substrate, thus would be equivalent (See MPEP 2183).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over (Ayel et al. (US PGPUB 2022/0093807, hereinafter referred to as “Ayel”) as applied to claim 1 above, and further in view of (Ayel et al. (US PGPUB 2022/0093807, hereinafter referred to as “Ayel”).
Ayel fails to explicitly show, in claim 12, wherein the dielectric layer has a thickness in a range of about 0.2 microns to about 0.3 microns.
Ayel teaches forming a dielectric layer for the purpose of improving the collection of the charges generated in depth in the substrate ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the dielectric layer has a thickness in a range of about 0.2 microns to about 0.3 microns, in the device of Ayel, according to the teachings of Ayel, with the motivation of improving the collection of the charges generated in depth in the substrate.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 9, 2026