DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 4/08/26. Currently, claims 1-3, 7-18, and 20-24. Claim 20 withdrawn and claims 21-24 are newly added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-18, and 20-24, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PGPub 2022/0102404, hereinafter referred to as “Lee”).
Lee teaches the semiconductor device as claimed. See figures 3A-3E and corresponding text, where Lee teaches, in claim 1, a structure comprising:
a semiconductor substrate (302) including a trench (306), the trench surrounding a portion of the semiconductor substrate (302), and the trench having a sidewall;
a deep trench isolation region (302) including a dielectric layer and a semiconductor layer inside the trench, the dielectric layer between the sidewall of the trench and the semiconductor layer; and
a first active device field-effect transistor (217) including a gate on the semiconductor layer, a first doped source/drain region in the semiconductor layer, and a second doped source/drain region in the semiconductor layer (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 2, comprising:
a single-photon avalanche diode including a terminal in the portion of the semiconductor substrate (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 3, further comprising:
a metal feature configured to connect the first doped source/drain region of the first active device field-effect transistor to the terminal of the single-photon avalanche diode (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 7, wherein the semiconductor layer comprises single-crystal silicon (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 8, wherein the semiconductor layer comprises amorphous silicon (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 9, wherein the semiconductor layer comprises polycrystalline silicon (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 10, wherein the dielectric layer of the deep trench isolation region fully surrounds the portion of the semiconductor substrate (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 11, wherein the trench includes a bottom, and the semiconductor layer is in direct contact with the semiconductor substrate at the bottom of the trench (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 12, wherein the dielectric layer has a thickness in a range of about 0.2 microns to about 0.3 microns (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 13, wherein the sidewall of the trench fully surrounds the portion of the semiconductor substrate (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 14, wherein the semiconductor substrate has a top surface, the semiconductor layer has a top surface that is coplanar with the top surface of the semiconductor substrate, and the first doped source/drain region of the first active device field-effect transistor is disposed adjacent to the top surface of the semiconductor layer (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 15, wherein the first doped source/drain region of the first active device field-effect transistor is coextensive with the top surface of the semiconductor layer (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 16, wherein the first doped source/drain region of the first active device field-effect transistor extends from the top surface of the semiconductor layer to a first depth in the semiconductor substrate, and the trench extends from the top surface of the semiconductor substrate to a second depth that is greater than the first depth (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 17, wherein the trench has a closed shape (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 18, further comprising:
a second active device field-effect transistor including a first doped source/drain region in the semiconductor layer (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 21, wherein the second field-effect transistor includes a gate on the semiconductor layer, and a second doped source/drain region in the semiconductor layer (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 22, wherein the gate of the first field-effect transistor fully surrounds a perimeter of the single-photon avalanche detector (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 23, wherein the first source/drain region and the second source/drain region of the first field-effect transistor fully surround the perimeter of the single- photon avalanche detector (figures 3A-3E; [0091-0100]).
Lee teaches, in claim 24, wherein the gate of the first field-effect transistor comprises a layer stack including a gate electrode and a gate dielectric layer, the gate electrode comprises a conductor, and the gate dielectric layer comprises an electrical insulator (figures 3A-3E; [0091-0100]).
Response to Arguments
Applicant’s arguments, see Remarks, filed 04/08/26, with respect to the rejection(s) of claim(s) 1-3, 7-18, and 20-24 Ayel et al. (US PGPub 2022/0093807, hereinafter referred to as “Ayel”) under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al. (US PGPub 2022/0102404, hereinafter referred to as “Lee”).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 June 14, 2026
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