DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Page 13, paragraph 60, last sentence: Double check that the ratio is 1:4 to 1:12. From the context of the sentence, it appears that the ratio should be 4:1 to 12:1.
Appropriate correction is required.
Claim Objections
Claim 14 is objected to because of the following informalities:
Claim 14, line 2: Double check that the ratio is 1:4 to 1:12. In light of the specification, it appears that the ratio should be 4:1 to 12:1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 14, and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Shin, U.S. Pat. Pub. No. 2021/0118618, Figure 1A and 1B.
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Regarding claim 1: Shin Figures 1A and 1B disclose a logic device, comprising: a substrate (110); at least one first insulating layer (122) on the substrate (110), the at least one first insulating layer (122) including a plurality of through-holes (122H) therein; a second insulating layer (140) on the at least one first insulating layer (122); and a capacitor portion (120, CB1, 130, 154) in the at least one first insulating layer (122) and the second insulating layer (140), the capacitor portion (120, CB1, 130, 154) including a capacitor structure (CB1) with a lower electrode (132), a dielectric film (134), and an upper electrode (136), and the capacitor structure (CB1) continuously extending inside the plurality of through-holes (122H) of the at least first insulating layer (122) and along an upper surface of the at least one first insulating layer (122) around each of the plurality of through-holes (122H). Shin specification ¶¶ 23-40.
Regarding claim 2, which depends from claim 1: Shin discloses the lower electrode (132) conformally extends inside the plurality of through-holes (122H) and along the upper surface of the at least one first insulating layer (122) around each of the plurality of through-holes (122H), the dielectric film (134) conformally extends along the lower electrode (132), and the upper electrode (136) conformally extends along the dielectric film (134). Id. ¶ 27.
Regarding claim 3, which depends from claim 1: Shin discloses the capacitor portion (120, CB1, 130, 154) further includes an interconnect member (130) on the capacitor structure (132, 134, 136), the interconnect member (130) including: a first area having a plurality of filling plugs (130B) filling the plurality of through-holes (122H) on the capacitor structure (132, 134, 136), and a second area having a plate member (130A) electrically connecting the plurality of filling plugs (130B). Id. ¶ 31.
Regarding claim 4, which depends from claim 3: Shin discloses the capacitor portion (120, CB1, 130, 154) further includes a lower plate layer (120) and an upper plate layer (154). Id. ¶¶ 24, 31, 32.
Regarding claim 5, which depends from claim 4: Shin discloses the capacitor structure (CB1) is on the lower plate layer (120), and the upper plate layer (154) is on the interconnect member (130). Id.
Regarding claim 6, which depends from claim 1: Shin discloses the lower electrode (132) and the upper electrode (136) include TiN. Id. ¶ 29.
Regarding claim 7, which depends from claim 1: Shin discloses the dielectric film (134) includes at least one of Zr oxide, Al oxide, and Ti oxide. Id. ¶ 30 (listing all three oxides among others).
Regarding claim 8: Shin Figures 1A and 1B disclose a logic device, comprising: a substrate (110); at least one first insulating layer (122) on the substrate (110), the at least one first insulating layer (122) including a plurality of through-holes (122H); a second insulating layer (140) on the at least one first insulating layer (122); wires (142, 144) in the at least one first insulating layer (122) and the second insulating layer (140); and a capacitor portion (120, CB1, 130, 154) in the at least one first insulating layer (122) and the second insulating layer (140), the capacitor portion (120, CB1, 130, 154) including: a lower plate layer (120), a first portion (142) of the wires (142, 144) being electrically connected to the lower plate layer (120), a capacitor structure (CB1) on the lower plate layer (120), the capacitor structure (CB1) continuously extending along an upper surface of the lower plate layer (120), an inner surface of the plurality of through-holes (122H), and an upper surface of the at least one first insulating layer (122) around each of the plurality of through-holes (122H), an interconnect member (130) on the capacitor structure (CB1), and an upper plate layer (154) on the interconnect member (130), a second portion (144) of the wires (142, 144) being electrically connected to the upper plate layer (154). Id. ¶¶ 23-40.
Regarding claim 14, which depends from claim 8: Shin Figures 1A and 1B disclose that a ratio of a width of each of the plurality of through-holes to a width of the capacitor structure is 1:4 to 1:12. See Shin Figures 1A and 1B.
Regarding claim 16: Shin Figures 1A and 1B disclose a manufacturing method of a logic device, the method comprising: forming a lower plate layer (120) and a first insulating layer (122) on a substrate (110), such that the lower plate layer (120) is between the substrate (110) and the first insulating layer (122); forming a plurality of through-holes (122H) in the first insulating layer (122) to expose the lower plate layer (120); forming a capacitor structure (132, 134, 136) in the plurality of through-holes (122H) of the first insulating layer (122), such that the capacitor structure (132, 134, 136) continuously extends along an upper surface of the lower plate layer (120) exposed by the plurality of through-holes (122H), along inner surfaces of the plurality of through-holes (122H), and an upper surface of the first insulating layer (122); forming a plurality of filling plugs (130A) filling the capacitor structure (132, 134, 136) in the plurality of through-holes (122H), and depositing a plate member (130A) connecting the plurality of filling plugs (130B) on the plurality of filling plugs (130B); depositing an upper plate layer (154) on the plate member (130A); and forming a first wire (MW2) connected to the upper plate layer (154) and a second wire (142, MW1) connected to the lower plate layer (120). Shin specification ¶¶ 23-40.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson, U.S. Pat. No. 6,417,535, Figures 1-13, 24C, and 25C, and further in view of Jin, U.S. Pat. Pub. No. 2003/0183862, Figures 4A-4F.
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Regarding claim 1: Johnson Figures 1-13, 24C, and 25C disclose a capacitor device, comprising: a substrate (not shown); at least one first insulating layer (middle inter-layer dielectric material (40)) on the substrate, the at least one first insulating layer (middle (40)) including a plurality of through-holes (80) therein; a second insulating layer (upper inter-layer dielectric material (40)) on the at least one first insulating layer (middle (40)); and a capacitor portion (32) in the at least one first insulating layer (middle (40)) and the second insulating layer (upper (40)), the capacitor portion (32) including a capacitor structure (42, 44, 62) with a lower electrode (42), a dielectric film (44), and an upper electrode (62), and the lower electrode (42) and the dielectric film (44) of the capacitor structure (42, 44, 62) continuously extending inside the plurality of through-holes (80) of the at least first insulating layer (middle (40)) and along an upper surface of the at least one first insulating layer (middle (40)) around each of the plurality of through-holes (80). Johnson specification, col. 4, l. 63 - col. 11, l. 59; col. 14, l. 44 – col. 15, l. 23. Johnson does not disclose that the upper electrode (62) of the capacitor structure (42, 44, 62) continuous extends inside the plurality of through-holes (80) of the at least first insulating layer (middle (40)) and along an upper surface of the at least one first insulating layer (middle (40)) around each of the plurality of through-holes (80). Johnson also does not specifically state that the capacitor device is a logic device.
Jin Figures 4A-4F, directed to similar subject matter, disclose a logic device, comprising: a substrate (not shown); at least one first insulating layer (56) on the substrate, the at least one first insulating layer (56) including a plurality of through-holes (60) therein; and a capacitor portion (52a, 68, 70a) in and on the at least one first insulating layer (56), the capacitor portion (52a, 68, 70a) including a capacitor structure (68) with a lower electrode (62), a dielectric film (64), and an upper electrode (66), and the capacitor structure (68) continuously extending inside the plurality of through-holes (60) of the at least first insulating layer (56) and along an upper surface of the at least one first insulating layer (56) around each of the plurality of through-holes (60). Jin specification ¶¶ 37-53. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Johnson to include the Jin capacitor structure design because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 2, which depends from claim 1: The combination discloses the lower electrode (Johnson (42); Jin (62)) conformally extends inside the plurality of through-holes (Johnson (80); Jin (60)) and along the upper surface of the at least one first insulating layer (Johnson middle (40); Jin (56)) around each of the plurality of through-holes (Johnson (80); Jin (60)), the dielectric film (Johnson (44); Jin (64)) conformally extends along the lower electrode (Johnson (42); Jin (62)), and the upper electrode (Jin (66)) conformally extends along the dielectric film (Johnson (44); Jin (64)). Johnson specification, col. 4, l. 63 - col. 11, l. 59; col. 14, l. 44 – col. 15, l. 23; Jin specification ¶¶ 37-53.
Regarding claim 3, which depends from claim 1: The combination discloses the capacitor portion (Johnson (32); Jin (52a, 68, 70a)) further includes an interconnect member (Johnson (70, 38); Jin (70a)) on the capacitor structure (Johnson (42, 44 62)); Jin (68)), the interconnect member (Johnson (70, 38); Jin (70a)) including: a first area having a plurality of filling plugs (Johnson (70); plug portion of Jin (70a)) filling the plurality of through-holes (Johnson (80); Jin (60)) on the capacitor structure (Johnson (42, 44, 62)); Jin (68)), and a second area having a plate member (Johnson (38); plate portion of Jin (70a)) electrically connecting the plurality of filling plugs (Johnson (70); plug portion of Jin (70a)). Id.
Regarding claim 6, which depends from claim 1: Jin discloses that the lower electrode and the upper electrode include TiN. Jin specification ¶ 47. Johnson discloses the lower electrode (42) includes TiN, Johnson, col. 8, ll. 15-23, and states that the upper electrode material (100) which is etched to form upper electrode (62) may be of the same type of metal as lower electrode (42), id. col. 10, ll. 43-46; col. 11, ll. 11-13.
Regarding claim 7, which depends from claim 1: Jin discloses the dielectric film (64) includes at least one of Zr oxide, Al oxide, and Ti oxide. Jin specification ¶ 48 (zirconium oxide; two types of titanium oxide).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson and Jin, and further in view of Dirnecker, U.S. Pat. Pub. No. 2002/0163029, Figures 1-10, and Won, U.S. Pat. Pub. No. 2005/0087879, Figures 1-13.
Dirnecker, Figures 1-4:
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Dirnecker, Figures 5-10:
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Won, Figures 1-7:
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Won, Figures 8-13:
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Regarding claim 4, which depends from claim 3: Johnson discloses the capacitor portion (32) further includes a lower plate layer (38), but is silent as to the presence of an upper plate layer.
Dirnecker, Figures 1-10, directed to similar subject matter, discloses a logic device, comprising: a substrate; at least one first insulating layer on the substrate (104), the at least one first insulating layer (104) including a plurality of through-holes therein; and a capacitor portion (106, 112, 132, 152, 162, lower metal layer of second metal layer (182)) in the at least one first insulating layer (104), the capacitor portion (106, 112, 132, 152, 162, lower portion of second metal layer (182)) including a capacitor structure (112, 132, 152) with a lower electrode (112), a dielectric film (132), and an upper electrode (152), and the dielectric film (132) of the capacitor structure (112, 132, 152) continuously extending inside the plurality of through-holes of the at least first insulating layer (104) and along an upper surface of the at least one first insulating layer (104) around each of the plurality of through-holes; wherein the capacitor portion (106, 112, 132, 152, 162, lower portion of second metal layer (182)) further includes an interconnect member (162, lower portion of second metal layer (182)) on the capacitor structure (112, 132, 152), the interconnect member (162, lower portion of second metal layer (182)) including: a first area having a plurality of filling plugs (162) filling the plurality of through-holes on the capacitor structure (112, 132, 152), and a second area having a plate member (lower portion of second metal layer (182)) electrically connecting the plurality of filling plugs (162); the capacitor portion (106, 112, 132, 152, 162, lower portion of second metal layer (182)) further includes a lower plate layer (106) and an upper plate layer (upper portion of second metal layer (182)). Dirnecker specification ¶¶ 55-62. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Dirnecker design as the plate member of the interconnect member and the upper plate layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Won, directed to similar subject matter, discloses interconnect layers (55, 77) with a similar structure as the Dirnecker metal layers (106, 182). See Won Figure 13; Won specification ¶¶ 33-43. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Won design because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses that the Dirnecker plate member (lower portion of second metal layer (182)) of the capacitor structure second area corresponds to the Won diffusion barrier layer (77a) and main conductive layer (77b), the Dirnecker lower plate layer (106) of the capacitor portion corresponds to Won lower interconnect layer (55), and the Dirnecker upper plate layer (upper portion of second metal layer (182)) corresponds to Won diffusion capping layer (77c).
Regarding claim 5, which depends from claim 4: The combination discloses the capacitor structure (Johnson (42, 44, 62); Dirnecker (112, 132, 152); Won (61a, 65, 67a)) is on the lower plate layer (Johnson (38); Dirnecker (106); Won (55)), and the upper plate layer (Won (77c); upper portion of Dirnecker (182)) is on the interconnect member (Won (77a, 77b), 69a (first area of interconnect member in Won); Dirnecker (162), lower portion of Dirnecker (182))).
Claims 8-10 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson, and further in view of Jin, Dirnecker, Won, and Kang, U.S. Pat. Pub. No. 2015/0364474.
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Regarding claim 8: Johnson Figures 1-13, 24C, and 25C, disclose a capacitor device, comprising: a substrate (not shown); at least one first insulating layer (middle interlayer dielectric layer (40)) on the substrate, the at least one first insulating layer (middle (40)) including a plurality of through-holes (80); a second insulating layer (upper interlayer dielectric layer (40)) on the at least one first insulating layer (middle (40)); wires (lower, middle, and upper layers (36)) in the at least one first insulating layer (middle (40)) and the second insulating layer (upper (40)); and a capacitor portion (32) in the at least one first insulating layer (middle (40)) and the second insulating layer (upper (40)), the capacitor portion (32) including: a lower plate layer (middle (38)), a first portion of the wires (not shown) being electrically connected to the lower plate layer (middle (38)), a capacitor structure (42, 44, 62) on the lower plate layer (38), the capacitor structure (42, 44, 62) continuously extending along an upper surface of the lower plate layer (middle (38)), an inner surface of the plurality of through-holes (80), and the lower electrode (42) and the dielectric layer (44) continuously extending along an upper surface of the at least one first insulating layer (middle (40)) around each of the plurality of through-holes (80), an interconnect member (70, upper (38)) on the capacitor structure (42, 44, 62), and a second portion (unshown) of the wires (36) being electrically connected to the interconnect member (70, upper (38)). Johnson specification, col. 4, l. 63 - col. 11, l. 59; col. 14, l. 44 – col. 15, l. 23. Johnson does not disclose that the upper electrode (62) of the capacitor structure (42, 44, 62) continuous extends inside the plurality of through-holes (80) of the at least first insulating layer (middle (40)) and along an upper surface of the at least one first insulating layer (middle (40)) around each of the plurality of through-holes (80). Johnson also does not specifically state that the capacitor device is a logic device. Lastly, Johnson does not disclose an upper plate layer.
Jin Figures 4A-4F, directed to similar subject matter, disclose a logic device, comprising: a substrate (not shown); at least one first insulating layer (56) on the substrate, the at least one first insulating layer (56) including a plurality of through-holes (60) therein; and a capacitor portion (52a, 68, 70a) in and on the at least one first insulating layer (56), the capacitor portion (52a, 68, 70a) including: a lower plate layer (52a), a capacitor structure (68) on the lower plate layer (52a), the capacitor structure (68) continuously extending along an upper surface of the lower plate layer (52a), an inner surface of the plurality of through-holes (60), and an upper surface of the at least first insulating layer (56) around each of the plurality of through-holes (60), and an interconnect member (70a) on the capacitor structure (68). Jin specification ¶¶ 37-53. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Johnson to include the Jin capacitor structure design because the modification would have involved the substitution of an equivalent known for the same purpose.
Dirnecker, Figures 1-10, directed to similar subject matter, discloses a logic device, comprising: a substrate; at least one first insulating layer on the substrate (104), the at least one first insulating layer (104) including a plurality of through-holes therein; and a capacitor portion (106, 112, 132, 152, 162, lower metal layer of second metal layer (182)) in the at least one first insulating layer (104), the capacitor portion (106, 112, 132, 152, 162, lower portion of second metal layer (182)) including: a lower plate layer (106), a capacitor structure (112, 132, 152) on the lower plate layer (106), with a lower electrode (112), a dielectric film (132), and an upper electrode (152), and the dielectric film (132) of the capacitor structure (112, 132, 152) continuously extending inside the plurality of through-holes of the at least first insulating layer (104) and along an upper surface of the at least one first insulating layer (104) around each of the plurality of through-holes; an interconnect member (162, lower portion of second metal layer (182)) on the capacitor structure (112, 132, 152), and an upper plate layer (upper portion of second metal layer (182)) on the interconnect member (162, lower portion of second metal layer (182)). Dirnecker specification ¶¶ 55-62. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Dirnecker design as the plate member of the interconnect member and the upper plate layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Won, directed to similar subject matter, discloses interconnect layers (55, 77) with a similar structure as the Dirnecker metal layers (106, 182). See Won Figure 13; Won specification ¶¶ 33-43. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Won design because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses that the Dirnecker plate member (lower portion of second metal layer (182)) of the capacitor structure second area corresponds to the Won diffusion barrier layer (77a) and main conductive layer (77b), the Dirnecker lower plate layer (106) of the capacitor portion corresponds to Won lower interconnect layer (55), and the Dirnecker upper plate layer (upper portion of second metal layer (182)) corresponds to Won diffusion capping layer (77c).
Lastly, Kang Figure 22, directed to similar subject matter, discloses a capacitor device, comprising: a substrate (100); at least one first insulating layer (190) on the substrate (100), the at least one first insulating layer (190) including a plurality of through-holes; a second insulating layer (230) on the at least one first insulating layer (190); wires (234, 232) in the at least one first insulating layer (190) and the second insulating layer (230); and a capacitor portion (182, 202, 212, 222) in the at least one first insulating layer (190) and the second insulating layer (230), the capacitor portion (182, 202, 212, 222) including: a lower plate layer (182), a first portion (234) of the wires (232, 234) being electrically connected to the lower plate layer (182), a capacitor structure (202, 212, 222) on the lower plate layer (182), the capacitor structure (202, 212, 222) continuously extending along an upper surface of the lower plate layer (182), an inner surface of the plurality of through-holes, and an upper surface of the at least one first insulating layer (190) around each of the plurality of through-holes, an upper electrode (222) having a plate-like upper portion, a second portion (232) of the wires (232, 234) being electrically connected to the plate-like upper portion. Kang specification ¶¶ . One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Kang wiring connections because Kang teaches how to make an electrical connection to the upper and lower capacitor electrodes. This renders obvious claim 8.
Regarding claim 9, which depends from claim 8: Won discloses that the lower plate layer (55) and the upper plate layer (77c) include TiN. See Won specification ¶¶ 35, 36.
Regarding claim 10, which depends from claim 8: Johnson discloses that the interconnect member (70a, 38) includes Al. Johnson specification, col. 6, ll. 30-38. See also Jin specification ¶¶ 52-53 (describing interconnect member (70a) as being formed the same as bottom interconnection conductive layer (52)), 39 (details on forming bottom interconnection conductive layer (52)).
Regarding claim 14, which depends from claim 8: Johnson discloses a ratio of a width of each of the plurality of through-holes (80) to a width of the capacitor structure (32) is 1:4 to 1:12. See Johnson Figures 1, 25A.
Regarding claim 15, which depends from claim 8: The combination discloses the capacitor portion is included in a back end of line. Dirnecker specification ¶ 25.
Regarding claim 16: Johnson Figures 1-13, 24C, and 25C disclose a manufacturing method of a capacitor device, the method comprising: forming a lower plate layer (38) and a first insulating layer (middle interlayer dielectric material (40)) on a substrate (not shown), such that the lower plate layer (38) is between the substrate and the first insulating layer (middle (40)); forming a plurality of through-holes (80) in the first insulating layer (middle (40)) to expose the lower plate layer (38); forming a capacitor structure (42, 44, 62) in the plurality of through-holes (80) of the first insulating layer (middle (40)), such that the capacitor structure (42, 44, 62/100) continuously extends along an upper surface of the lower plate layer (38) exposed by the plurality of through-holes (80), along inner surfaces of the plurality of through-holes (80), and an upper surface of the first insulating layer (middle (40)); forming a plurality of filling plugs (70) filling the capacitor structure (42, 44, 62) in the plurality of through-holes (80), and depositing a plate member (60) connecting the plurality of filling plugs (70) on the plurality of filling plugs (70). Johnson specification, col. 4, l. 63 - col. 11, l. 59; col. 14, l. 44 – col. 15, l. 23. Johnson does not disclose that its device is a logic device. Johnson does not disclose depositing an upper plate layer on the plate member. Johnson discusses electrical connections to the capacitor, but does not specifically disclose forming a first wire connected to the upper plate layer and a second wire connected to the lower plate layer.
Jin Figures 4A-4F, directed to similar subject matter, discloses a capacitor device as a part of a logic device. Jin specification ¶ 2. Johnson removes part of its upper electrode layer (100) so that the resulting upper electrode (62) does not continuously extend along an upper surface of the first insulating layer, but Jin discloses this feature in its capacitor, specifically: forming a lower plate layer (52a) and a first insulating layer (56) on a substrate (not shown), such that the lower plate layer (52a) is between the substrate and the first insulating layer (56); forming a plurality of through-holes (60) in the first insulating layer (56) to expose the lower plate layer (52a); forming a capacitor structure (68) in the plurality of through-holes (60) of the first insulating layer (56), such that the capacitor structure (68) (lower electrode (62), capacitor dielectric (64), and upper electrode (66)) continuously extends along an upper surface of the lower plate layer (38) exposed by the plurality of through-holes (60), along inner surfaces of the plurality of through-holes (60), and an upper surface of the first insulating layer (56); forming a plurality of filling plugs (portion of upper interconnection (70a)) in through-holes (60) that remain after capacitor structure (68) is formed)) filling the capacitor structure (68) in the plurality of through-holes (60), and depositing a plate member (plate portion of upper interconnection (70a)) connecting the plurality of filling plugs (portion of upper interconnection (70a)) on the plurality of filling plugs (portion of upper interconnection (70a)). Jin specification ¶¶ 37-53. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Johnson to include the Jin capacitor structure design because the modification would have involved the substitution of an equivalent known for the same purpose.
Dirnecker Figures 1-10, directed to similar subject matter, discloses a manufacturing method of a logic device, the method comprising: forming a lower plate layer (106) and a first insulating layer (104) on a substrate (not shown), such that the lower plate layer (106) is between the substrate and the first insulating layer (104); forming a plurality of through-holes in the first insulating layer (104) to expose the lower plate layer (106); forming a capacitor structure (112, 132, 152) in the plurality of through-holes of the first insulating layer (104), such that the capacitor structure (112, 132, 152) continuously extends along an upper surface of the lower plate layer (106) exposed by the plurality of through-holes, along inner surfaces of the plurality of through-holes, and, for dielectric layer (132) and upper electrode (152), an upper surface of the first insulating layer (104); forming a plurality of filling plugs (162) filling the capacitor structure (112, 132, 152) in the plurality of through-holes, and depositing a plate member (lower portion of second metal layer (182)) connecting the plurality of filling plugs (162) on the plurality of filling plugs (162); depositing an upper plate layer (upper portion of second metal layer (182)) on the plate member (lower portion of second metal layer (182)). Dirnecker specification ¶¶ 55-62. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Dirnecker design as the plate member of the interconnect member and the upper plate layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Won, directed to similar subject matter, discloses interconnect layers (55, 77) with a similar structure as the Dirnecker metal layers (106, 182). See Won Figure 13; Won specification ¶¶ 33-43. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Won design because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses that the Dirnecker plate member (lower portion of second metal layer (182)) of the capacitor structure second area corresponds to the Won diffusion barrier layer (77a) and main conductive layer (77b), the Dirnecker lower plate layer (106) corresponds to Won lower interconnect layer (55), and the Dirnecker upper plate layer (upper portion of second metal layer (182)) corresponds to Won diffusion capping layer (77c).
Lastly, Kang Figure 22, directed to similar subject matter, discloses forming a first wire (232) connected to an upper plate layer (222)/upper capacitor electrode and a second wire (234) connected to a lower plate layer (182), which is connected to the lower capacitor electrode (202B). Kang specification ¶¶ 155-165. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Kang design because the modification shows how to make an electrical connection to the capacitor.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson, Jin, Dirnecker, Won, and Kang, and further in view of Jin Figures 8A-8I.
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Regarding claim 11, which depends from claim 8: The combination is silent as to the presence of an etch-stop layer between the capacitor structure and the upper surface of the at least one first insulating layer around each of the plurality of through-holes.
Jin Figures 8A-8I, directed to similar subject matter, disclose the use of an etch-stop layer (180) between the capacitor structure (190) and the upper surface of the at least one first insulating layer (178) around each of the plurality of through-holes (182). Jin specification ¶¶ 99-115. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the etch-stop layer in the claimed location because the etch-stop layer would protect lower layers during later deposition and etching processes.
Regarding claim 12, which depends from claim 11: Jin discloses the etch-stop layer includes SiN. Id. ¶ 104.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson, Jin, Dirnecker, Won, and Kang, and further in view of Chen, U.S. Pat. Pub. No. 2016/0071802.
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Regarding claim 17, which depends from claim 16: Kang shows vias (232, 234) as the first and second wires, but Kang is silent as to how the vias are formed.
Chen Figure 1, discussing prior art, discloses a via (14) formed by a single damascene process. Chen specification ¶ 16. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use a single damascene process to form the first and second wires (232, 234) because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming each of the first wire and the second wire by a single damascene process.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson, Jin, Dirnecker, Won, and Kang and further in view of Huang, U.S. Pat. No. 11,245,000, Figure 2, and Chen.
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Regarding claim 18, which depends from claim 16: Kang shows vias (232, 234) as the first and second wires, but Kang is silent as to how the vias are formed.
Huang Figure 2, directed to similar subject matter, discloses via and trench connections (C1, C2) to the lower plate/conductive layer (110) which the capacitor (BE, CD, TE) is on and electrically connected to, and to the upper electrode (TE) of the capacitor (BE, CD, TE). Huang specification, col. 3, l. 31 – col. 5, l. 50. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to replace the Kang connections with the Huang connections because the modification because the modification would have involved the substitution of an equivalent known for the same purpose.
Chen Figure 1, discussing prior art, discloses via-trench connections (24, 26) that are formed by a dual damascene process. Id. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use a dual damascene process to form the first and second wires (Kang (232, 234), as modified by Huang) because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming the first wire and the second wire by a dual damascene process.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson, Jin, Dirnecker, Won, and Kang, and further in view of Hsu, U.S. Pat. Pub. No. 2019/0252349, Figures 1-11, and Chen.
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Regarding claim 19, which depends from claim 16: The combination does not disclose after forming the lower plate layer and the first insulating layer on the substrate, such that the lower plate layer is between the substrate and the first insulating layer, forming a plurality of wires by a dual damascene process.
Hsu Figures 1-11, directed to similar subject matter, disclose after forming the equivalent of the lower plate layer (160a, 160b) and the first insulating layer (140b) on the substrate (102), such that the lower plate layer (160a, 160b) is between the substrate (102) and the first insulating layer (140b), forming a plurality of wires (contact (112) in dielectric layer (140b), followed by contact (112) formed in dielectric layer (140a)), Hsu specification ¶¶ 20-26, with a trench and a via. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use Hsu wire formation process because the modification provides electrical connections to devices in the substrate (102).
Chen Figure 1, discussing prior art, discloses connections (24, 26) that are formed, trench and via, by a dual damascene process. Chen specification ¶ 16. Thus, the combination discloses after forming the lower plate layer and the first insulating layer on the substrate, such that the lower plate layer is between the substrate and the first insulating layer, forming a plurality of wires by a dual damascene process.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Dirnecker and Won.
Regarding claim 9, which depends from claim 8: Shin discloses that the lower plate layer (120) may include tungsten and the upper plate layer (154) include TiN. Shin specification ¶¶ 24, 32. Shin does not disclose that the lower plate layer (120) includes TiN.
Dirnecker, Figures 1-10, directed to similar subject matter, discloses a logic device, comprising: a substrate; at least one first insulating layer on the substrate (104), the at least one first insulating layer (104) including a plurality of through-holes therein; and a capacitor portion (106, 112, 132, 152, 162, lower metal layer of second metal layer (182)) in the at least one first insulating layer (104), the capacitor portion (106, 112, 132, 152, 162, lower portion of second metal layer (182)) including: a lower plate layer (106), a capacitor structure (112, 132, 152) on the lower plate layer (106), with a lower electrode (112), a dielectric film (132), and an upper electrode (152), and the dielectric film (132) of the capacitor structure (112, 132, 152) continuously extending inside the plurality of through-holes of the at least first insulating layer (104) and along an upper surface of the at least one first insulating layer (104) around each of the plurality of through-holes; an interconnect member (162, lower portion of second metal layer (182)) on the capacitor structure (112, 132, 152), and an upper plate layer (upper portion of second metal layer (182)) on the interconnect member (162, lower portion of second metal layer (182)). Dirnecker specification ¶¶ 55-62. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the Shin to include the Dirnecker design as the plate member of the interconnect member and the upper plate layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Won, directed to similar subject matter, discloses interconnect layers (55, 77) with a similar structure as the Dirnecker metal layers (106, 182). See Won Figure 13; Won specification ¶¶ 33-43. The lower plate (55) has a diffusion barrier layer (55a) and a capping layer (55c) that may be TiN, Won specification ¶ 35, and the upper plate (77) has a diffusion barrier layer (77a) and a capping layer (77c) that have the same materials as their corresponding lower plate layers, id. ¶ 36. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Won design because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses that the Dirnecker plate member (lower portion of second metal layer (182)) of the capacitor structure second area corresponds to the Won diffusion barrier layer (77a) and main conductive layer (77b), the Dirnecker lower plate layer (106) of the capacitor portion corresponds to Won lower interconnect layer (55), which includes TiN, and the Dirnecker upper plate layer (upper portion of second metal layer (182)) corresponds to Won diffusion capping layer (77c), which includes TiN.
Regarding claim 15, which depends from claim 8: The combination discloses the capacitor portion is included in a back end of line. Dirnecker specification ¶ 25.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Johnson or Jin.
Regarding claim 10, which depends from claim 8: Shin discloses that the interconnect member (130) includes silicon germanium. Shin specification ¶ 24. Shin does not disclose that the interconnect member includes Al.
Johnson, directed to similar subject matter, discloses that the interconnect member (70, 38) includes Al. Johnson specification, col. 6, ll. 30-38. Jin, directed to similar subject matter, discloses its interconnect member (70a) comprises aluminum. See Jin specification ¶¶ 52-53 (describing interconnect member (70a) as being formed the same as bottom interconnection conductive layer (52)), 39 (details on forming bottom interconnection conductive layer (52), including aluminum). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin to use either the Johnson or Jin materials because the modification would have involved a selection of a known material based on its suitability for its intended use.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Jin.
Regarding claim 11, which depends from claim 8: Shin is silent as to the presence of an etch-stop layer between the capacitor structure (CB1) and the upper surface of the at least one first insulating layer (122) around each of the plurality of through-holes (122H).
Jin Figures 8A-8I, directed to similar subject matter, disclose the use of an etch-stop layer (180) between the capacitor structure (190) and the upper surface of the at least one first insulating layer (178) around each of the plurality of through-holes (182). Jin specification ¶¶ 99-115. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin to use the etch-stop layer in the claimed location because the etch-stop layer would protect lower layers during later deposition and etching processes.
Regarding claim 12, which depends from claim 11: Jin discloses the etch-stop layer includes SiN. Id. ¶ 104.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Kang and Chen.
Regarding claim 17, which depends from claim 16: Shin shows vias (142, 162) and wiring layers (152, 164) as the first and second wires (first wire: 142, MW1 (152, 162, 164); second wire (MW2 (162, 164)), but Shin is silent as to how the vias and wiring layers are formed.
Kang Figure 22, directed to similar subject matter, discloses forming a first wire (232) connected to an upper plate layer (222)/upper capacitor electrode and a second wire (234) connected to a lower plate layer (182), which is connected to the lower capacitor electrode (202B). Kang specification ¶¶ 155-165. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin to include the Kang design because the modification shows an alternate method to make an electrical connection to the capacitor.
Chen Figure 1, discussing prior art, discloses a via (14) formed by a single damascene process. Chen specification ¶ 16. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin/Kang to use a single damascene process to form the first and second vias (232, 234) because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming each of the first wire and the second wire by a single damascene process.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Chen.
Regarding claim 18, which depends from claim 16: Shin shows vias (142, 162) and wiring layers (152, 164) as the first and second wires (first wire: 142, MW1 (152, 162, 164); second wire (MW2 (162, 164)), but Shin is silent as to how the vias and wiring layers are formed. Wires (162, 164) appear to be trench-via formations in Shin Figure 1A.
Chen Figure 1, discussing prior art, discloses trench-via connections (24, 26) that are formed by a dual damascene process. Id. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin to use a dual damascene process to form the first and second wires because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined, the combination discloses forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming the first wire and the second wire by a dual damascene process.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shin, and further in view of Hsu and Chen.
Regarding claim 19, which depends from claim 16: Shin does not disclose after forming the lower plate layer (120) and the first insulating layer (122) on the substrate (110), such that the lower plate layer (120) is between the substrate (110) and the first insulating layer (120), forming a plurality of wires (142, 144, MW1: 152, 162, 164; MW2: 162, 164),but Shin is silent as to whether these wires are formed by a dual damascene process. Some of the wires (162, 164) appear to be formed as by forming a trench and then a via, or vice versa.
Hsu Figures 1-11, directed to similar subject matter, disclose after forming the equivalent of the lower plate layer (160a, 160b) and the first insulating layer (140b) on the substrate (102), such that the lower plate layer (160a, 160b) is between the substrate (102) and the first insulating layer (140b), forming a plurality of wires (contact (112) in dielectric layer (140b), followed by contact (112) formed in dielectric layer (140a)), Hsu specification ¶¶ 20-26, with a trench and a via. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Shin to use Hsu wire formation process because the modification provides electrical connections to devices in the substrate (102).
Chen Figure 1, discussing prior art, discloses connections (24, 26) that are formed, trench and via, by a dual damascene process. Chen specification ¶ 16. Thus, the combination discloses after forming the lower plate layer and the first insulating layer on the substrate, such that the lower plate layer is between the substrate and the first insulating layer, forming a plurality of wires by a dual damascene process.
Allowable Subject Matter
Claims 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 13: The claim has been found allowable because the prior art of record does not disclose “a ratio of a width of each of the plurality of through-holes to a width of each of the wires is 1:5 to 1:10”, in combination with the remaining limitations of the claim.
With regard to claim 20: The claim has been found allowable because the prior art of record does not disclose “after depositing the upper plate layer on the plate member, etching the capacitor structure, the plate member, and the upper plate layer in an area in which the plurality of wires are formed”, in combination with the remaining limitations of the claim.
Conclusion
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/Victoria K. Hall/Primary Examiner, Art Unit 2897