DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Species I and VIII in the reply filed on November 10, 2025 is acknowledged.
In the telephonic interview January 21, 2026, Applicant affirmed that Species I being elected to comply with the restriction requirement. Applicant identified claims 1-6, 8-9 and 11-20 are readable on the elected Species.
Claims 1-20 are pending. Non-elected Species, claims 7 and 10 have been withdrawn from consideration.
Hover, claim 16 recites: …, wherein a width of the first inner gate structure in the first direction is smaller than a width of the second inner gate structure in the first direction.
Thus, claim 16 directed to non-elected Species.
Therefore, claim 16 has been effectively withdrawn from consideration.
Action on merits of claims 1-6, 8-9, 11-15 and 17-20 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 16, 2023 and May 20, 2024 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SEMICONDUCTOR DEVICE HAVING A SILICIDE MASK PATTERN AND A CONTACT SILICIDE FILM FORMED BETWEEN SOURCE/DRAIN PATTERN AND SOURCE/DRAIN CONTACT
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-9, 11-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (EP. Pub. No. 4 009 377) of record.
With respect to claim 1, KIM teaches a semiconductor device substantially as claimed including:
an active pattern (AP) extending in a first direction (D1);
a plurality of gate structures (GS1) on the active pattern (AP) and spaced apart in the first direction (D1), each of the plurality of gate structures (GS1) comprising a gate electrode (120) extending in a second direction (D2), and a gate spacer on side walls of the gate electrode (120);
a source/drain pattern (150) between adjacent ones of the plurality of gate structures;
a silicide mask pattern (upper portion of 175) on the source/drain pattern (150), the silicide mask pattern comprising an upper surface and a bottom surface opposite to each other in a third direction (D3), the upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode (120);
a source/drain contact (180) on the source/drain pattern (150) and connected to the source/drain pattern (150); and
a contact silicide film (lower portion of 175) between the source/drain contact (180) and the source/drain pattern (150), the contact silicide film (lower portion of 175) contacting the bottom surface of the silicide mask pattern (upper portion of 175),
wherein a height from a lowermost part of the source/drain pattern (150) to a lowermost part of the source/drain contact (180) and a height from the lowermost part of the source/drain pattern (150) to the bottom surface of the silicide mask pattern (upper portion of 175). (See FIG. 34).
Thus, KIM is shown to teach all the features of the claim with the exception of explicitly disclosing the height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than the height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern (upper portion of 175).
However, regarding the “silicide mask pattern” and “contact silicide pattern”, as a semiconductor device, the “silicide mask pattern” and “contact silicide pattern” are parts, upper and lower portions, of an interface pattern formed between the source/drain patterns 150 and the source/drain contacts 180. The upper portion 160 is defined as “silicide mask pattern” and the lower portion (155) is defined as “contact silicide pattern”.
Similarly, the interface pattern 175 of KIM is formed between the source/drain patterns 150 and the source/drain contacts 180. The pattern 175 of KIM, thus, can be similarly defined as upper portion of 175 and lower portion of 175. In which, the upper portion of 175 is identified as “silicide mask pattern” and the lower portion of 175 is identified as “contact silicide pattern”.
The “upper surface” of the upper portion of 175 is determined as the “upper surface of the silicide mask pattern” and the “bottom surface” of the upper portion 175 is determined as below the top surface of GS1-_INT.
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Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the upper portion of 175 or the silicide mask pattern of KIM extends from upper surface of 175 to a point below the uppermost inner gate structure GS-_INT to form the semiconductor device without alter the scope of KIM.
With respect to claim 2, the source/drain contact (180) of KIM covers the upper surface of the silicide mask pattern.
With respect to claim 3, the height from the lowermost part of the source/drain pattern (150) of KIM to the bottom surface of the silicide mask pattern (upper portion of 175) is smaller than the height from the lowermost part of the source/drain pattern to an upper surface of the active pattern (150).
With respect to claim 4, the height from the lowermost part of the source/drain pattern (150) to the upper surface of the silicide mask pattern (upper portion of film 175) is greater than the height from the lowermost part of the source/drain pattern (150) to an upper surface of the active pattern (AP).
With respect to claim 5, a respective side wall (185) of the source/drain contact of KIM is in contact with a side wall (140) of a respective gate structure (GS1) of the plurality of gate structures.
With respect to claim 6, the source/drain contact (180) of KIM has a single conductive film structure.
With respect to claim 8, the active pattern (AP) of KIM comprises a lower pattern (BP) extending in the first direction (D1) and a plurality of sheet patterns (NS) spaced apart from the lower pattern (BP) in the third direction (D3), and
wherein each of the plurality of gate structures (GS1) comprises an inner gate structure between the lower pattern (BP) and the sheet pattern (NS), and between adjacent sheet patterns (NS) of the plurality of sheet patterns.
With respect to claim 9, each of the plurality of gate structures (GS1) of KIM comprises a gate insulating film (130), and wherein each gate insulating film (130) included in a respective inner gate structure (120) contacts the source/drain pattern (150).
With respect to claim 11, KIM teaches a semiconductor device substantially as claimed including:
an active pattern (AP1) comprising a lower pattern (BP) extending in a first direction (D1), and a plurality of sheet patterns (NS) spaced apart from the lower pattern (BP) in a second direction (D3), the plurality of sheet patterns (NS) comprising an uppermost sheet pattern;
a plurality of gate structures (GS1) on the lower pattern (BP) spaced apart in a first direction (D1), each of the plurality of gate structures comprising a gate electrode (120) extending in a third direction (D2);
a source/drain pattern (150) on the lower pattern (BP) and connected to the sheet pattern (NS);
a silicide mask pattern (upper portion of 175) on the source/drain pattern (150), the silicide mask pattern comprising an upper surface and a bottom surface opposite to each other in the second direction (D3), the upper surface of the silicide mask pattern being higher than an upper surface of the uppermost sheet pattern, and lower than an upper surface of the gate electrode (120);
a source/drain contact (180) on the source/drain pattern (150) and connected to the source/drain pattern; and
a contact silicide film (lower portion of 175) between the source/drain contact (180) and the source/drain pattern (150), the contact silicide film contacting the bottom surface of the silicide mask pattern (upper portion of 175). (See FIG. 34).
Thus, KIM is shown to teach all the features of the claim with the exception of explicitly disclosing the contact silicide film contacting the bottom surface of the silicide mask pattern.
However, see claim 1 above, the upper portion of film 175 can be seen as and meet the “silicide mask pattern” and the lower portion of film 175 can be seen as and meet the “contact silicide film”, hence, the contact silicide film (lower portion of film 175) contacting the bottom surface of the silicide mask pattern (upper portion of film 175).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the upper portion of film 175 of KIM being the silicide mask pattern and the lower portion of film 175 being the contact silicide film contacting each other to form the semiconductor device without alter the scope of KIM.
With respect to claim 12, a height from the lowermost part of the source/drain pattern (150) to the bottom surface of the silicide mask pattern (upper portion of film 175) is smaller than a height from the lowermost part of the source/drain pattern (150) to an upper surface of the active pattern (AP).
With respect to claim 13, each of the plurality of gate structures of KIM comprises a plurality of inner gate structures between the lower pattern (BP) and a lowermost sheet pattern (NS1) of the plurality of sheet patterns, and between adjacent ones of the plurality of sheet patterns,
wherein each of the plurality of inner gate structures comprises an uppermost inner gate structure that is in contact with a bottom surface of the uppermost sheet pattern, and
wherein the bottom surface of the silicide mask pattern (upper portion of film 175) is lower than the upper surface of the uppermost inner gate structure, and is higher than the bottom surface of the uppermost inner gate structure. (See FIG. 34 above).
With respect to claim 14, each of the plurality of gate structures (GS1) of KIM comprises a gate spacer on a side wall of the gate electrode (120), and wherein a side wall (185) of the source/drain contact (180) is in contact with an outer side wall (140) of the gate spacer.
With respect to claim 15, the source/drain contact (180) of KIM covers the upper surface of the silicide mask pattern (upper portion of film 175).
With respect to claim 17, each of the plurality of gate structures (GS1) of KIM comprises a plurality of inner gate structures between the lower pattern (BP1) and a lowermost sheet pattern (NS1) of the plurality of sheet patterns, and between adjacent ones of the plurality of sheet patterns,
wherein the plurality of inner gate structures comprises a first inner gate structure, and a second inner gate structure between the lower pattern (BP1) and the first inner gate structure, and
wherein a width of the first inner gate structure in the first direction (D1) is the same as a width of the second inner gate structure in the first direction (D1).
With respect to claim 18, KIM teaches a semiconductor device substantially as claimed including
an active pattern (AP) comprising:
a lower pattern (BP) extending in a first direction (D1), and
a plurality of sheet patterns (NS) spaced apart from the lower pattern (BP) in a second direction (D3), the plurality of sheet patterns (NS) comprising an uppermost sheet pattern;
a plurality of gate structures (GS1-) on the lower pattern (BP) spaced apart in the first direction (D1), each of the plurality of gate structures comprising a gate electrode (120) extending in a third direction (D2) and a gate spacer on a side wall of the gate electrode (120);
a source/drain pattern (150) on the lower pattern (BP) and connected to the sheet pattern;
a silicide mask pattern (upper portion of film 175) on the source/drain pattern (150), the silicide mask pattern comprising an upper surface and a bottom surface opposite to each other in the second direction (D3);
a source/drain contact (l80) on the source/drain pattern (150), the source/drain contact being in contact with the upper surface of the silicide mask pattern (upper portion of film 175), a side wall (185) of the source/drain contact (180) being in contact with an outer side wall (140) of the gate spacer; and
a contact silicide film (lower portion of film 175) between the source/drain contact (180) and the source/drain pattern (150), the contact silicide film (lower portion of film 175) being in contact with the bottom surface of the silicide mask pattern (upper portion of film 175),
wherein each of the plurality of gate structures (GS) comprises a plurality of inner gate structures disposed between the lower pattern (BP) and the plurality of sheet patterns (NS), and between adjacent ones of the plurality of sheet patterns (NS),
wherein each of the plurality of inner gate structures comprises an uppermost inner gate structure (GS1_INT) in contact with a bottom surface of the uppermost sheet pattern, and
wherein the bottom surface of the silicide mask pattern (upper portion of film 175) is lower than the upper surface of the uppermost inner gate structure (GS1_INT), and is higher than the bottom surface of the uppermost inner gate structure (GS1_INT). (See FIG. 34).
Regarding the “silicide mask pattern” and “contact silicide film”, see claims 1 and 11 above.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the bottom surface of the silicide mask pattern (upper portion of film 175) of KIM being lower than the upper surface of the uppermost inner gate structure, and higher than the bottom surface of the uppermost inner gate structure to form the semiconductor device without alter the scope of KIM.
With respect to claim 19, the upper surface of the silicide mask pattern (upper portion of film 175) of KIM is higher than the upper surface of the uppermost sheet pattern.
With respect to claim 20, each of the plurality of gate structures of KIM comprises a gate insulating film (130), and wherein the gate insulating film (130) included in each of the plurality of inner gate structures is in contact with the source/drain pattern (150).
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893