Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-15 in the reply filed on 11/25/2025 is acknowledged.
Claim 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/25/2025.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Izuka (JP 2013014805 A).
PNG
media_image1.png
676
804
media_image1.png
Greyscale
CLAIM 1. Izuka discloses a multi-chip semiconductor package comprising:
an interconnect layer (Izuka Fig. 4) having an upper surface and a bottom surface, wherein said interconnect layer comprises a dielectric material 5, at least one common source1 pad 3-4 disposed on said upper surface of said interconnect layer (Figs. 3-4 Note: Interconnect layer is the layers located over singulated chips 2.);
at least one common gate pad 4-4 disposed on said upper surface of said interconnect layer; and a plurality of semiconductor devices 2 (Fig. 3) each comprising a gate pad 4 and at least one source pad 3 adhered onto said interconnect layer (Figs. 2-4);
wherein said source pads 3 of said plurality of semiconductor devices 2 (Izuka Fig 2) are electrically connected to said at least one common source pad 3-4, and wherein said source pads 3 of said plurality of semiconductor devices 2 are electrically connected in parallel with one another (Izuka figs. 3) ; and
wherein said gate pads 4-1(4) of said plurality of semiconductor devices 2are electrically connected to said common gate pad 4-4, and wherein said gate pads of said plurality of semiconductor devices are electrically connected in parallel with one another (Izuka, Figs. 3 & 4 – Element 3-4 is shown to connected each of the source electrodes of each device, and 4-4 is shown to connected each of the gate electrodes 4. As such they are understood to be in parallel.)
PNG
media_image2.png
804
506
media_image2.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-10, 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izuka (JP 2013014805 A) in view of Hohlfeld et al (US 20160126212 A1)
CLAIM 2. Izuka disclose a multi-chip semiconductor package of claim 1, however may be silent upon the capability of the device further comprising an adhesive layer disposed on said bottom surface of said interconnect layer.
While Izuka does not explicitly state that the material layer at the surface interface is an adhesive, the use of adhesive layers to bond interconnects to semiconductor devices was well-known and practiced at the time of the invention.
Hohlfeld teaches the structurally analogous device as recited in claim 1 and as applied in view of Izuka, Hohlfeld however further discloses the use of additional layers 15 and 11 located between an interconnect layer and semiconductor devices (Hohlfeld, Figs. 36-43). Specifically, Hohlfeld explicitly discloses that layer 11 is an adhesive (Hohlfeld fig.s 28-29 & ¶ [0031], [0035]). Furthermore, Hohlfeld’s layer 13 is a passivation layer similar to layer 5 of Izuka. It is noted that such passivation layers are understood to adhere to surrounding layers by some finite amount, thereby meeting the broad scope of "an adhesive” or material having adhesive properties.
It would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to recognize that the surface interface of Izuka (e.g., layer 5) would necessarily include an adhesive or a material possessing adhesive properties. Alternatively, it would have been obvious to modify Izuka in view of Hohlfeld to include an additional adhesive layer at the surface interface to provide improved adhesion between the interconnect and the semiconductor components.
PNG
media_image3.png
852
586
media_image3.png
Greyscale
This modification represents the application of a known technique (incorporating adhesive layers for component bonding) to a known device ready for improvement (the semiconductor assembly of Izuka) to yield predictable results (improved structural integrity). Such a combination is considered obvious under the guidelines set forth in KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007).
CLAIM 3. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 1 further comprising a plurality of gate contacts disposed on said interconnect layer and electrically connected to said common gate pad by trace connections, wherein each gate pad of each of said plurality of semiconductor devices is connected to an associated gate contact of said plurality of gate contacts (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28 – source-21/gate-70).
CLAIM 4. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 3, wherein said plurality of gate contacts are equidistant (e.g. in vertical/z direction) from said common gate pad (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28 – source-21/gate-70).
CLAIM 5. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 3, wherein said gate trace connections have an equal resistivity value (Resistivity is an intrinsic property of a material. Since the gate trace connections are fabricated from the same conductive material (shown to be integral in figures), they would possess an equal resistivity value regardless of their individual lengths or cross-sectional areas.).
CLAIM 6. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 5, wherein at least one trace connection of said trace connections comprises one of a surface-mount resistor and a thin- film resistor (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28).
CLAIM 7. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 3, wherein said common gate pad and said at least one common source pad are configured to be electrically connected to external power electronic circuitry such that said a POL-RDL package operates as a singular processing unit (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28 Note: The limitation "configured to be electrically connected... such that [it] operates as a singular processing unit" fails to provide a patentable structural distinction over the prior art. This recitation is a functional statement of intended use that does not impose any unique physical geometry or structural modification on the gate and source pads. Because the prior art discloses identical structural components—specifically transistors connected in parallel—it is inherently capable of being connected to external circuitry to function as a singular unit in the same manner. Under MPEP 2114, an apparatus claim that is structurally identical to the prior art is not rendered patentable by simply reciting a function or intended use of which the prior art is already capable.).
CLAIM 8. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 7 further comprising a Kelvin contact electrically connected to said at least one common source pad to facilitate connecting said at least one common source pad to the external power electronic circuitry (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28 Note: The recitation of a "Kelvin contact" fails to provide a patentable structural distinction over the prior art, as the term is merely a functional designation suggesting an intended use for a standard electrical contact. The specification provides no specific teaching that the Kelvin contact possesses a unique physical structure or geometry that differs from any other conductive contact or terminal. Because the claim fails to define any specific structural limitations for the contact, and the prior art discloses conductive contacts connected to source pads, the prior art structure is inherently capable of being utilized as a Kelvin contact. Under MPEP 2114, a structural component is not rendered patentable by reciting a name that merely suggests a function or intended use of which the prior art is already capable.)
CLAIM 9. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 1, further comprising: an additional interconnect layer 51-1 disposed over said interconnect layer 44-(1-3); a package gate pad 53-1 disposed on said additional interconnect layer 51-1 and electrically connected to said common gate pad 44 of said interconnect layer 44-(1-3); and at least one package source pad (not labeled but shown above 43-3) disposed on said additional interconnect layer (not labeled but shown above 43-3 in same level as 51-1) and electrically connected to said at least one common source pad 33 of said interconnect layer (Izuka Figure 14 demonstrates the application of an additional interconnect layer over a device structure analogous to the embodiment shown in Figures 2-4. It would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to modify the device of Figures 2-4 in view of the teaching in Figure 14 to include additional interconnect layers and pads. Such a modification represents the combination of known features disclosed within a single reference to achieve predictable electrical connectivity. Combining multiple embodiments from the same prior art patent—particularly those shown to be compatible—does not require "a leap of inventiveness" (Boston Scientific Scimed, Inc. v. Cordis Corp., 554 F.3d 982 (Fed. Cir. 2009)).)
PNG
media_image4.png
582
392
media_image4.png
Greyscale
CLAIM 10. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 9, wherein said package gate pad is electrically connected to a gate attachment pad by a trace connection 54-2, said gate attachment pad connected to said common gate pad of said interconnect layer (Izuka Figure 14).
CLAIM 12. (Currently Amended) The multi-chip semiconductor package of claim 9, wherein said package gate pad and said at least one package source pad are configured to be electrically connected to external power electronic circuitry such that said aPOL-RDL package operates as a singular power switching unit (Both Izuka figs. 2-4 & Hohlfeld Figs. 28-28 Note: The limitation "configured to be electrically connected... such that [it] operates as a singular processing unit" fails to provide a patentable structural distinction over the prior art. This recitation is a functional statement of intended use that does not impose any unique physical geometry or structural modification on the gate and source pads. Because the prior art discloses identical structural components—specifically transistors connected in parallel—it is inherently capable of being connected to external circuitry to function as a singular unit in the same manner. Under MPEP 2114, an apparatus claim that is structurally identical to the prior art is not rendered patentable by simply reciting a function or intended use of which the prior art is already capable.).
CLAIM 13. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 1, wherein a surface area of said interconnect layer is substantially equal to a surface area of a footprint defined by the plurality of semiconductor devices (Izuka Figs. 2-4 and Hohlfeld Fig. 28-29 both demonstrate the relative structural relationship as claimed.).
CLAIM 14. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 1, wherein a backside of the semiconductor devices are electrically connected together by an electrically conductive plate such that a common drain connection is formed (Izuka – “backside electrode 46 – Fig. 14 & 66-Fig. 16 & Hohlfeld Fig. 28 – element 22 Note: the backside of these 3-terminal devices by design is understood to be the drain side.).
CLAIM 15. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 14 further comprising a molding disposed between said interconnect layer and said electrically conductive plate (Izuka Figs. 2-4 & Hohlfeld Fig. 28 – element 4).
While Izuka does not clearly depict molding material between the individual chips in its figures, the use of such a material is taught understood from the translated specificatoin. Izuka describes the structure using an "insulating protective film 5," which is preferably made of "polyimide resin or epoxy resin" and insulates the main electrode 3 and control electrode 4 in each “singulated” chip region (Izuka). These materials are standard encapsulants or molding compounds used in semiconductor packaging.
Hohlfeld depicts an analogous device structure and further demonstrates that individual “singulated” laminated chips, arranged similarly to those in Izuka, utilize a molding material extending between the chips to provide structural integrity and insulation (Hohlfeld, Fig. 28).
It would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to modify the laminated chip arrangement of Izuka to explicitly include molding material extending between the chips as taught by Hohlfeld. This represents a simple substitution of one known element (an epoxy or polyimide molding material/film) for another to obtain the predictable result of structural stability and electrical isolation. Such a combination of known elements is considered obvious under the guidelines of KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izuka in view of Hohlfeld et al (US 20160126212 A1) in view of Geller et al. (US 20090267079 A1).
CLAIM 11. Izuka in view of Hohlfeld discloses a multi-chip semiconductor package of claim 10, however may be silent upon wherein said trace connection electrically connected to said package gate pad comprises one of a surface- resistor and a thin-film resistor, the use of integrated resistors in the gate paths of parallel-connected power transistors was well-known in the art at the time of the invention.
Geller teaches a scalable power semiconductor device structure (analogous to Izuka) wherein a plurality of transistors are interconnected in parallel. Geller explicitly discloses that the structure may comprise passive electronic components, such as gate bias resistors (323, 325), integrated with each active component to enable precise control of the gate terminal voltage (Geller at ¶ [0044] and Fig. 3A). The use of surface-resistors or thin-film resistors for such gate bias applications is a standard manufacturing choice for integrated RDL or overlay structures.
PNG
media_image5.png
506
556
media_image5.png
Greyscale
PNG
media_image6.png
702
514
media_image6.png
Greyscale
It would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to modify the gate trace connections of the Izuka/Hohlfeld device to include a surface or thin-film resistor as taught by Geller. This modification represents the application of a known technique (integrating gate resistors) to a known device ready for improvement (the parallel-connected FETs of Izuka) to yield predictable results (improved gate voltage control and signal balancing). Such a combination is considered obvious under the guidelines of KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
12/23/2025
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Izuka –“ As shown in FIG. 2, a main electrode 3 and a control electrode 4 are provided in each individual chip region 1 on one main surface (hereinafter referred to as a front surface) of the singulated element portion 2. . The main electrode 3 is, for example, an emitter electrode or a source electrode. The control electrode 4 is a gate electrode, for example. The main electrode 3 and the control electrode 4 provided in each individual chip region 1 are insulated from each other by an insulating protective film 5. The insulating protective film 5 is preferably made of polyimide resin or epoxy resin (the same applies to constituent materials of first to fourth insulating protective films 5-1 to 5-5 described later).”