DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the claims filled on 8/16/2023 that has been entered, wherein claims 1-16 are pending.
Election/Restrictions
Applicant's election with traverse of Invention I, claims 1-7 in the reply filed on 11/28/2025 is acknowledged. The traversal is on the ground(s) that no appropriate explanation was given in the Office Action with respect to MPEP § 808.02 sections. More particularly, when reading p. 2 of the outstanding Office Action, no such specific and detailed explanation exists of: (1) separate classification thereof; (2) separate status in the art when they are classifiable together; or (3) a different field of search, as required by the MPEP. The Office Action merely stated in general that "[i]n the instant case the product of claim 1 can be made by another and materially different process, then the process of claim 8, wherein the device of claim 1 can be made by conventional oven based mass reflow instead of thermal compression bonding." Therefore, Applicant believes that the Office Action failed to adequately explain reasons why there would allegedly be a serious burden on the Examiner if the restriction is not required. In view of the foregoing, Applicant submits that all inventions have sufficient unity of invention, so that all claims should remain pending in the present application.
This is not found persuasive because page 3 of the restriction requirement states there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: Inventions I and II have acquired a separate status in the art as evidenced by their different classification.
The requirement is still deemed proper and is therefore made FINAL.
Claims 8-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement filed on 11/21/2024 and 8/16/2023 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the word “firs” in line 5. It appears “firs” should be “first”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation of “ the package structure in accordance with claim 4” in line 1 and “a plurality of upper RDL pads of the second upper surface are connected to the plurality of first solder bumps, the second lower surface of the second RDL is the active surface of the first electronic component, and the plurality of lower RDL pads are the plurality of conductors of the first electronic component” in line 5. Claim 4 defines “the exposed surface of the first encapsulate is the active surface of the first electronic component, and the plurality of first solder bumps are the plurality of conductors of the first electronic component” in line 6. Furthermore, claim 1, from which both claim 4 and 5 depend, requires “two adhesive surfaces of the adhesive layer are configured to be adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively” in line 11. It is unclear how both the second lower surface of the second RDL and the exposed surface of the first encapsulate can both be the active surface of the first electronic component when the a plurality of upper RDL pads of the second upper surface are connected to the plurality of first solder bumps? Additionally, how can both the plurality of lower RDL pads and the plurality of first solder bumps be the plurality of conductors of the first electronic component and exposed on the active surface, as required by claim 1, when the plurality of upper RDL pads of the second upper surface are connected to the plurality of first solder bumps? Claim 4 appears to be directed to Fig. 1, however claim 5 appears to be directed to Fig. 4 and should depend directly on claim 1. For the purpose of examination, “the package structure in accordance with claim 4” will be interpreted as “the package structure in accordance with claim 1” and “the plurality of first solder bumps” in line 6 will be interpreted as “a plurality of first solder bumps”.
Claims 6-7 depend on claim 5 and inherit it’s deficiencies.
Claim 6 recites the limitation "both sides of the plurality of second solder bumps" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination “"both sides of the plurality of second solder bumps" will be interpreted as “a first side and a second side of the plurality of second solder bumps”.
Claims 7 depend on claim 6 and inherit it’s deficiencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibata et al. (US 2022/0246488 A1).
Regarding claim 1, Shibata teaches a package structure(Fig. 5M) comprising:
a first redistribution layer (RDL)(6, ¶0014) including a first upper surface and a first lower surface, the first upper surface includes a plurality of upper bumps(63, ¶0014),
and the first lower surface includes a plurality of conductive pads(61, ¶0067);
an adhesive layer(70, ¶0014) located on the firs upper surface of the first RDL(6, ¶0014) and configured to surround the plurality of upper bumps(63, ¶0014); and
a first electronic component(50, ¶0014) disposed on the adhesive layer(70, ¶0014) and including an active surface(CS, ¶0014) and a plurality of conductors(41B, 42B, ¶0014), the active surface(CS, ¶0014) faces toward the first upper surface of the first RDL(6, ¶0014), and each of the plurality of conductors(41B, 42B, ¶0014) is exposed on the active surface(CS, ¶0014) and connected to one of the plurality of upper bumps(63, ¶0014), wherein two adhesive surfaces of the adhesive layer(70, ¶0014) are configured to be adhered to the first upper surface of the first RDL(6, ¶0014) and the active surface(CS, ¶0014) of the first electronic component(50, ¶0014), respectively.
Regarding claim 2, Shibata teaches the package structure in accordance with claim 1, wherein the adhesive layer(70, ¶0014) is an organic adhesive material(¶0056, ¶0018, epoxy resin, acrylic resin).
The step of the adhesive layer(70, ¶0014) is formed by curing an organic adhesive material(¶0056, ¶0018, epoxy resin, acrylic resin) is considered to be a process limitation are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 3, Shibata teaches the package structure in accordance with claim 1 further comprising a plurality of conductive components(7, ¶0067), wherein each of the plurality of conductive components(7, ¶0067) is located on the first lower surface of the first RDL(6, ¶0014) and configured to be connected to one of the plurality of conductive pads(61, ¶0067).
Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US 2022/0328391 A1).
Regarding claim 1, Hu teaches a package structure(Fig. 3G) comprising:
a first redistribution layer (RDL)(130, ¶0069) including a first upper surface(S3) and a first lower surface, the first upper surface(S3) includes a plurality of upper bumps(140, ¶0068),
and the first lower surface includes a plurality of conductive pads(185, ¶0075);
an adhesive layer(150, ¶0073) located on the first upper surface(S3) of the first RDL(130, ¶0069) and configured to surround the plurality of upper bumps(140, ¶0068); and
a first electronic component(110, 180a, 170,160, ¶0079,¶0080) disposed on the adhesive layer(150, ¶0073) and including an active surface(S1) and a plurality of conductors(116, ¶0071), the active surface(S1) faces toward the first upper surface(S3) of the first RDL(130, ¶0069), and each of the plurality of conductors(116, ¶0071) is exposed on the active surface(S1) and connected to one of the plurality of upper bumps(140, ¶0068), wherein two adhesive surfaces of the adhesive layer(150, ¶0073) are configured to be adhered to the first upper surface(S3) of the first RDL(130, ¶0069) and the active surface(S1) of the first electronic component(110, 180a, 170,160, ¶0079,¶0080), respectively.
Regarding claim 3, Hu teaches the package structure in accordance with claim 1 further comprising a plurality of conductive components(195, ¶0078), wherein each of the plurality of conductive components(195, ¶0078) is located on the first lower surface of the first RDL(130, ¶0069) and configured to be connected to one of the plurality of conductive pads(185, ¶0075).
Regarding claim 5, Hu teaches the package structure in accordance with claim 4, wherein the first electronic component(110, 180a, 170,160, ¶0079,¶0080) further includes a second RDL(110, ¶0078), the second RDL(110, ¶0078) includes a second lower surface and a second upper surface, a plurality of lower RDL pads(116, ¶0071) of the second lower surface are connected to the plurality of upper bumps(140, ¶0068), a plurality of upper RDL pads(162, ¶0071) of the second upper surface are connected to a plurality of first solder bumps(120, ¶0068), the second lower surface of the second RDL(110, ¶0078) is the active surface(S1) of the first electronic component(110, 180a, 170,160, ¶0079,¶0080), and the plurality of lower RDL pads(116, ¶0071) are the plurality of conductors(116, ¶0071) of the first electronic component(110, 180a, 170,160, ¶0079,¶0080).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US 2022/0246488 A1).
Regarding claim 4, Shibata teaches the package structure in accordance with claim 1, wherein the first electronic component(50, ¶0014) further includes a first encapsulate(5, ¶0014), a first die(41A, 42A, ¶0014) and a plurality of first bumps(41B, 42B, ¶0014) located on the first die(41A, 42A, ¶0014), the first encapsulate(5, ¶0014) is configured to surround the first die(41A, 42A, ¶0014) and the plurality of first bumps(41B, 42B, ¶0014), a first connection surface of each of the plurality of first bumps(41B, 42B, ¶0014) is exposed from an exposed surface of the first encapsulate(5, ¶0014), the exposed surface of the first encapsulate(5, ¶0014) is the active surface(CS, ¶0014) of the first electronic component(50, ¶0014), and the plurality of first bumps(41B, 42B, ¶0014) are the plurality of conductors(41B, 42B, ¶0014) of the first electronic component(50, ¶0014).
Shibata does not explicitly state a plurality of first solder bumps(41B, 42B, ¶0014). However, Shibata teaches different bumps 63 can be lead-free solder(¶0054). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use lead-free solder for the first solder bumps, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. MPEP 2144.07
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2022/0328391 A1) in view of Lin et al. (US 20160343685 A1) and Shin (US 9,922,845 A1).
Regarding claim 6, Hu teaches the package structure in accordance with claim 5.
Hu is not relied on to teach an second electronic component and a third RDL, wherein the second electronic component includes a second encapsulate, a second die and a plurality of second solder bumps, the second die includes a lower conduction surface and an upper conduction surface, both sides of the plurality of second solder bumps are connected to the lower conduction surface of the second die and a plurality of upper conductive pads(185, ¶0075) of the third RDL respectively, the second encapsulate is configured to surround the second die and the plurality of second solder bumps, the upper conduction surface of the second die and a second connection surface of each of the plurality of second solder bumps are exposed from the second encapsulate, the upper conduction surface of the second die is connected to the plurality of conductive pads(185, ¶0075) of the first RDL(130, ¶0069).
Lin teaches a package structure(Fig. 3E) comprising an second electronic component(120B, 160, 110B, ¶0048) and a third RDL(200, ¶0051), wherein the second electronic component(120B, 160, 110B, ¶0048) includes a second encapsulate(120B, ¶0048), a second die(110B, ¶0037), the second die(110B, ¶0037) includes a lower conduction surface and an upper conduction surface, the second encapsulate(120B, ¶0048) is configured to surround the second die(110B, ¶0037), the upper conduction surface of the second die(110B, ¶0037) are exposed from the second encapsulate(120B, ¶0048), the upper conduction surface of the second die(110B, ¶0037) is connected to the plurality of conductive pads(pad portions of 140B contacting 160, ¶0043) of the first RDL(130B, ¶0042). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu, to include an second electronic component and a third RDL, wherein the second electronic component includes a second encapsulate, a second die, the second die includes a lower conduction surface and an upper conduction surface, the second encapsulate is configured to surround the second die, the upper conduction surface of the second die are exposed from the second encapsulate, the upper conduction surface of the second die is connected to the plurality of conductive pads of the first RDL as taught by Lin, so that more than two components or dies can be integrated in a semiconductor package assembly, where the sizes and/or functions of the components or dies are not limited resulting in improvements to the flexibility of the design and enchantment of the manufacturing yield of the semiconductor package assembly(¶0066).
Hu and Lin are not relied on to teach a plurality of second solder bumps, an first side and a second side of the plurality of second solder bumps are connected to the lower conduction surface of the second die and a plurality of upper conductive pads(pad portions of 140B contacting 160, ¶0043) of the third RDL(200, ¶0051) respectively, the second encapsulate(120B, ¶0048) is configured to surround the plurality of second solder bumps, a second connection surface of each of the plurality of second solder bumps are exposed from the second encapsulate(120B, ¶0048).
Shih teaches a package structure(Fig. 9) comprising a plurality of second solder bumps(320, col. 4, lines 42-55), an first side and a second side of the plurality of second solder bumps(320, col. 4, lines 42-55) are connected to the lower conduction surface of the second die(102, 101, col. 4, lines 56-64) and a plurality of upper conductive pads(204, col. 4, lines 31-41) of the third RDL(20, col. 4, lines 31-41) respectively, the second encapsulate(400, col. 5, lines 15-22) is configured to surround the plurality of second solder bumps(320, col. 4, lines 42-55), a second connection surface of each of the plurality of second solder bumps(320, col. 4, lines 42-55) are exposed from the second encapsulate(400, col. 5, lines 15-22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu, so include a plurality of second solder bumps, an first side and a second side of the plurality of second solder bumps are connected to the lower conduction surface of the second die and a plurality of upper conductive pads of the third RDL respectively, the second encapsulate is configured to surround the plurality of second solder bumps, a second connection surface of each of the plurality of second solder bumps are exposed from the second encapsulate, as taught by Shih, in order to matches the input/output (I/O) pad pitch on an active surface of the second semiconductor die and allow electrical connection to the third RDL layer(col. 4, lines 42-65).
Regarding claim 7, Hu teaches the package structure in accordance with claim 6.
Hu is not relied on to teach a plurality of conductive components, wherein the plurality of conductive components are connected to a plurality of lower conductive pads of the third RDL.
Lin teaches a package structure(Fig. 3E) comprising a plurality of conductive components(210, ¶0052), wherein the plurality of conductive components(210, ¶0052) are connected to a plurality of lower conductive pads(220, ¶0052) of the third RDL(200, ¶0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu, to include a plurality of conductive components, wherein the plurality of conductive components are connected to a plurality of lower conductive pads of the third RDL as taught by Lin, so that more than two components or dies can be integrated in a semiconductor package assembly, where the sizes and/or functions of the components or dies are not limited resulting in improvements to the flexibility of the design and enchantment of the manufacturing yield of the semiconductor package assembly(¶0066).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hwang et al. (US 20220037294 A1). Discoes an
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/LAURA M DYKES/Examiner, Art Unit 2892