Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 6, 8, 10-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf (PGPub No. 20220350079) in further view of Hsu (PGPub No. 20230061568) and Bruck (PGPub No. 20220260775).
Regarding claim 6, Aboketaf teaches a manufacturing method of an integrated structure of a waveguide and an active component, comprising: performing a substrate providing step comprising providing a substrate, wherein the substrate comprises a dielectric layer and a semiconductor layer disposed on the dielectric layer, and the semiconductor layer comprises a waveguide region, a transition region and an active component region (Fig. 3 points to a structure 10 comprising a waveguide core 14, a tapered section 40 (transition region), and a light absorbing layer 20 (active component region). [0019] further points to a dielectric layer 16 and a patterned semiconductor layer.); performing an ion implanting step comprising performing an ion implantation process on the semiconductor layer to form a first doped portion and a second doped portion in the active component region (Fig. 6 and [0030-31] point to doped regions 48 and 50 which may be formed by ion implantation); performing a semiconductor layer etching step comprising: etching the waveguide region to form a waveguide structure; etching the transition region to form a transition structure; and etching the first doped portion and the second doped portion to form an active component structure ([0019] points to the use of lithography and etching processes to pattern the waveguide core 14 (waveguide structure) and a pad 12, said pad being an area comprising the tapered section 40 (transition structure) and the doped regions 48 and 50 (active component structure).); performing a cover layer depositing step comprising depositing a cover layer on the dielectric layer, wherein the cover layer covers the waveguide structure, the transition structure, and the active component structure (Fig. 7 points to a dielectric layer 66.); and performing a via hole and contact pad forming step comprising forming two via holes connected to the active component structure in the cover layer, and respectively forming two contact pads on the two via holes (Id. points to contacts 68 and 70 (via holes). [0036] further points to the use of middle-of-line (MOL) processing and back-end-of-line (BEOL) processing, which includes formation of silicide, contacts (contact pads), vias (via holes), and wiring for an interconnect structure that is coupled with the photodetectors.).
Aboketaf fails to teach performing a trench forming step comprising etching the semiconductor layer to form a plurality of waveguide trenches in the waveguide region and the transition region of the semiconductor layer; performing a waveguide depositing step comprising depositing a waveguide material on the semiconductor layer to form a deposition layer on the semiconductor layer, wherein the waveguide trenches are filled with the waveguide material; and performing a deposition layer polishing step comprising performing a chemical-mechanical polishing process on the deposition layer to expose a surface in the semiconductor layer and the waveguide material filled in the waveguide trenches.
Hsu teaches performing a trench forming step comprising etching the semiconductor layer to form a plurality of waveguide trenches in the waveguide region and the transition region of the semiconductor layer (Figs. 6J points to an optical waveguide 600 comprising a plurality of trenches 626 separated by coupling gratings 625.); performing a waveguide depositing step comprising depositing a waveguide material on the semiconductor layer to form a deposition layer on the semiconductor layer, wherein the waveguide trenches are filled with the waveguide material (Fig. 7B and [0046] point to a semiconductor device 700 comprising a coupling layer 738 (deposition layer) which may be formed by depositing a waveguide material, e.g. silicon or silicon nitride, on various coupling gratings (plurality of waveguide trenches).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Aboketaf and Hsu, such that a plurality of waveguide trenches are formed and filled with a waveguide material in order to multiple waveguide regions that interrupt crack propagation and relieve accumulated stress.
Aboketaf et al. still fails to teach performing a deposition layer polishing step comprising performing a chemical-mechanical polishing process on the deposition layer to expose a surface in the semiconductor layer and the waveguide material filled in the waveguide trenches.
Bruck teaches performing a deposition layer polishing step comprising performing a chemical-mechanical polishing process on the deposition layer to expose a surface in the semiconductor layer and the waveguide material filled in the waveguide trenches ([0051] points to using a chemical mechanical polishing process to remove excess waveguide material (deposition layer) to complete the construction of a waveguide 120.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Bruck, such that a chemical-mechanical polishing process is performed on the deposition layer in order to lower optical loss of the waveguide through planarization.
Regarding claim 8, Aboketaf in combination with Hsu teaches wherein the semiconductor layer etching step further comprises: performing a mask disposing step comprising disposing a hard mask pattern on the surface to expose a first maskless pattern (Fig. 6F of Hsu points to a masking layer 640.); performing a first etching step to partially etch the first maskless pattern to form a plurality of first etching trenches and the active component structure, wherein an etching depth of each of the first etching trenches is the same as each other (Figs. 2-2A and [0019] of Aboketaf point to both the waveguide core 14 and the pad 12 (active component structure) being on the same dielectric layer 16 and patterned by lithography and etching processes. Fig. 6G of Hsu points to a plurality of trenches 646. It is considered obvious that both regions would be processed simultaneously in order to streamline the fabrication process.); performing a first photoresist forming step to form a first photoresist layer on a part of the transition region and a part of the active component region to expose a second maskless pattern; performing a second etching step to etch the second maskless pattern to form a plurality of second etching trenches and the transition structure, wherein an etching depth of each of the second etching trenches is the same as each other; performing a second photoresist forming step to remove the first photoresist layer and the hard mask pattern and form a second photoresist layer on the transition structure and the active component structure to shield the transition structure and the active component structure; and performing a third etching step to etch a third maskless pattern not shielded by the second photoresist layer to form the waveguide structure ([0019] of Aboketaf points to the waveguide core 14 and the pad 12 being patterned by lithography and etching processes. Figs.6F-6J, [0039], and [0043] of Hsu point to the formation of coupling gratings 625 (waveguide structure) comprising the patterned masking layer 640, which may comprise a photoresist (PR) material, and a multi-step etching process comprising at least two or three steps of etching. It is considered obvious that each step would also require their own PR material (first photoresist; second photoresist) in order to ensure the quality and control of each etching.). T Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Hsu, such that the semiconductor layer etching step comprises a series of etching steps utilizing photoresist layers in order to create a streamlined process that allows for the simultaneous etching of the waveguide, transition, and active component regions yet is also more controlled as each subsequent step focuses more on the formation of the waveguide structure.
Regarding claim 10, Aboketaf in combination with Hsu teaches wherein the semiconductor layer etching step further comprises: performing a mask disposing step to dispose a hard mask pattern on the surface to expose a first maskless pattern (Fig. 6F of Hsu points to a masking layer 640.); performing a first photoresist forming step to form a first photoresist layer on a part of the transition region and a part of the active component region to expose a second maskless pattern, wherein the second maskless pattern is a part of the first maskless pattern ([0039] of Hsu points to the masking layer 640 comprising a photoresist (PR) material.); performing a first etching step to etch the second maskless pattern to form a plurality of etching trenches and expose a first initial structure, a second initial structure and a third initial structure on the dielectric layer (Fig. 6G of Hsu points to a plurality of trenches 646 between a plurality of stacks 645 (initial structure(s)).); performing a second photoresist forming step to remove the first photoresist layer and form a second photoresist layer on the dielectric layer to cover the first initial structure, the second initial structure and the third initial structure; performing a second etching step to partially etch the part of the transition region not shielded by the second photoresist layer and the hard mask pattern to form a plurality of first etching trenches and the transition structure, and partially etch the part of the active component region not shielded by the second photoresist layer and the hard mask pattern to form a plurality of second etching trenches and the active component structure; performing a removing step to remove the second photoresist layer and the hard mask pattern to form and expose a first transition portion and a second transition portion of the transition structure and the active component structure on the dielectric layer; performing a third photoresist forming step to form a third photoresist layer on the transition structure and the active component structure to shield the transition structure and the active component structure; and performing a third etching step to etch a third maskless pattern not shielded by the third photoresist layer to form the waveguide structure and remove the third photoresist layer to expose the first transition portion and the second transition portion of the transition structure and the active component structure ([0019] of Aboketaf points to the waveguide core 14 and the pad 12 (transition structure; active component structure) being on the same dielectric layer 16 and patterned by lithography and etching processes. It is considered obvious that both regions would be processed simultaneously in order to streamline the fabrication process. Figs.6F-6J, [0039], and [0043] of Hsu point to the formation of coupling gratings 625 (waveguide structure) comprising the patterned masking layer 640, which may comprise a photoresist (PR) material, and a multi-step etching process comprising at least two or three steps of etching. It is considered obvious that each step would also require their own PR material (second photoresist; third photoresist) in order to ensure the quality and control of each etching.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Hsu, such that the semiconductor layer etching step comprises a series of etching steps utilizing photoresist layers in order to create a streamlined process that allows for the simultaneous etching of the waveguide, transition, and active component regions yet is also more controlled as each subsequent step focuses more on the formation of the waveguide structure.
Regarding claim 11, Aboketaf teaches wherein the waveguide structure, the transition structure and the active component structure are disposed between the dielectric layer and the cover layer, and connected to each in sequence (Figs. 3-4A point to the dielectric layer 16, dielectric layer 38 (cover layer), waveguide core 14 (waveguide structure), tapered section 40 (transition structure), and light absorbing layer 20 (active component structure).).
Regarding claim 13, Bruck teaches wherein the deposition layer is formed by a Chemical Vapor Deposition (CVD) process, and the waveguide material is silicon nitride (Si3N4) ([0074] points to the use of chemical vapor deposition to deposit a film of SiN.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Bruck, such that a CVD process is used to deposit the silicon nitride waveguide material in order to provide conformal deposition and/or excellent thickness control.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf et al. in further view of Lin (PGPub No. 20110294255).
Regarding claim 7, Hsu teaches performing a deep etching step to perform a deep etching process on the semiconductor layer to form the waveguide trenches in the waveguide region and the transition region of the semiconductor layer (Fig. 2J points to the deep trenches 626 which are formed by a multi-step etching process.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Meyer, such that a deep etching process is performed in order to create a deep etched waveguide, which is less lossy in passive material systems in comparison to a shallow etched waveguide.
Aboketaf et al. still fails to teach performing a hydrogen annealing step to perform a hydrogen annealing process on the waveguide trenches to smoothen the waveguide trenches.
Lin teaches performing a hydrogen annealing step to perform a hydrogen annealing process on the waveguide trenches to smoothen the waveguide trenches ([0024] points to performing hydrogen annealing on a silicon trench 16.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Lin, such that a hydrogen annealing step is performed in order to reduce the roughness of the trenches.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf et al. in further view of Chern (US Patent No. 11531159).
Regarding claim 9, Chern teaches wherein the mask disposing step further comprises: performing a mask depositing step to deposit a dielectric material on the surface to form a hard mask layer on the surface; performing a photolithography step to perform a photolithography process to form a photomask on the hard mask layer; and performing a mask etching step to shield a part of the hard mask layer through the photomask and etch the hard mask layer to form the hard mask pattern (Fig. 3 and Col. 4, lines 40-51 point to a hard mask layer that is patterned using photolithography and etch processes to form the first patterned hard mask 208.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Chern, such that a hard mask pattern is formed in order to create an etch mask to form trenches that define the underlying silicon features.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf et al. in further view of Bian (US Patent No. 10910503).
Regarding claim 12, Bian teaches wherein a material of the semiconductor layer is silicon, and a material of the dielectric layer and the cover layer is silicon dioxide (SiO2) (Fig. 1A points to a semiconductor device comprising a monocrystalline silicon layer 106 (semiconductor layer), a buried silicon dioxide layer 104 (dielectric layer), and a cladding structure 124 (cover layer) using silicon dioxide material.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Aboketaf et al. and Bian, such that a material of the semiconductor layer is silicon, and a material of the dielectric layer and the cover layer is silicon dioxide in order to create a silicon-on-insulator waveguide platform that enables compact low-loss photonic integrated circuits.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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