DETAILED ACTION
This Office action responds to Applicant’s amendment filed on 04/06/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0084993) in view of Lin (US 2012/0091574) in further view of Ting (US 2023/0307374).
Regarding claim 1, Kim shows (see, e.g., Kim: fig. 1B and annotated fig. 1B) most aspects of the instant invention including a semiconductor package 1, comprising:
A lower redistribution wiring layer 1000 having first redistribution wirings 110/210 stacked in at least two layers
A semiconductor chip 700 on the lower redistribution wiring layer 1000 and electrically connected to the first redistribution wirings 110/210
A sealing member 750 covering the semiconductor chip 700 on the lower redistribution wiring layer 1000
A plurality of through vias 930 penetrating the sealing member 750 and electrically connected to the first redistribution wirings 110/210
An upper redistribution wiring layer 2000 on the sealing member 750 and having second redistribution wirings 410/510 electrically connected to the plurality of through vias 930
Each of the first redistribution wirings 110/210 includes patterns sequentially stacked
However, Kim fails (see, e.g., Kim: figs. 1B and annotated fig. 1B) to show that the patterns include a barrier layer pattern, a seed pattern, and a plating pattern. Kim shows that the patterns include similar layers as the barrier/seed layer 11, and the metal pattern 621 made of a first metal pattern 621a, and a second metal pattern 621b (see, e.g., Kim: fig. 1C, and par. [0030], [0050]). Lin, in a similar device to Kim, shows (see, e.g., Lin: fig. 8B) that the patterns 200 include a barrier layer pattern 212, a seed pattern 214, and a plating pattern 220 (see, e.g., Lin: par. [0017], and [0021]). Lin also shows that these patterns 200 are modifications and arrangements to form delamination-free structures (see, e.g., Lin: par. [0004] and [0029]).
PNG
media_image1.png
905
1317
media_image1.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the patterns of Lin that include a barrier layer pattern, a seed pattern, and a plating pattern a in the device of Kim, in order to form delamination-free structures.
Kim in view of Lin shows (see, e.g., Lin: fig. 8B) that, viewed from a plan view, a sidewall of the barrier layer pattern 212 extends laterally beyond a sidewall of the seed layer pattern 214.
However, Kim in view of Lin fails (see, e.g., Kim: figs. 1B and annotated fig. 1B, and see, e.g., Lin: fig. 8B) to show that a thickness of the seed layer pattern 214 is within a range of 500 A to 1500 A. Ting, in a similar device to Kim in view of Lin, shows (see, e.g., Ting: fig. 4) that a thickness of the seed layer pattern (in the element 406) is within a range of 1000 A to 5000 A (a range of 100 nm to 500 nm) (see, e.g., Ting: par. [0089]). Ting also shows that the seed layer is deposited in order to form the redistribution wiring interconnects 406 (see, e.g., Ting: par. [0089]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the seed layer pattern of Ting in the device of Kim in view of Lin, in order to form the redistribution wiring interconnects.
However, the differences in the thicknesses of the seed layer pattern will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned thicknesses of the seed layer pattern, and Ting has identified such thicknesses of the seed layer pattern as result-effective variables subject to optimization (see, e.g., Ting: par. [0089]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Kim in view of Lin.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 2, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B and, and see, e.g., Lin: fig. 8B) that each of the first redistribution wirings 110/210 includes a recess configured by the sidewall of the seed layer pattern 214 recessed from a sidewall of the plating pattern 220 and the sidewall of the barrier layer pattern 212.
Regarding claim 3, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the sidewall of the barrier layer pattern 212 and the sidewall of the4 plating pattern 220 are vertically aligned with each other.
Regarding claim 4, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the barrier layer pattern 212 has a first thickness, the seed layer pattern 214 has a second thickness, and the plating pattern 220 has a third thickness greater than the first thickness and greater than the second thickness.
Regarding claim 6, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that the each of the first redistribution wirings 110/210 includes a redistribution via VH penetrating an underlying insulating layer 10/120, a redistribution pad L1 on the redistribution via V1/VH, and a redistribution line 110/210 extending from the redistribution pad L1 on the underlying insulating layer 10/120.
Regarding claim 8, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that the semiconductor chip 700 is mounted on the lower redistribution wiring layer 1000 via conductive bumps 708 (see, e.g., Kim: par. [0034]).
Regarding claim 9, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that the sealing member 750 exposes an upper surface of the semiconductor chip 700.
Regarding claim 10, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that a second package PK2 on the upper redistribution wiring layer 2000, wherein the second package comprises a package substrate 810 and at least one second semiconductor chip 800 stacked on the package substrate 810.
Regarding claim 11, Kim shows (see, e.g., Kim: fig. 1B) most aspects of the instant invention including a semiconductor package 1, comprising:
A lower redistribution wiring layer 1000 having first redistribution wirings 110/210 stacked in at least two layers
A semiconductor chip 700 on the lower redistribution wiring layer 1000, the semiconductor chip 700 having a first surface with chip pads 705 on the first surface, and the first surface facing lower redistribution wirings 110/210
A sealing member 750 covering the semiconductor chip 700 on the lower redistribution wiring layer 1000
A plurality of through vias 930 penetrating the sealing member 750 and electrically connected to the first redistribution wirings 110/210
An upper redistribution wiring layer 2000 on the sealing member 750
Each of the first redistribution wirings 110/210 includes patterns sequentially stacked
However, Kim fails (see, e.g., Kim: figs. 1B) to show that the patterns include a barrier layer pattern, a seed pattern, and a plating pattern. Kim shows that the patterns include similar layers as the barrier/seed layer 11, and the metal pattern 621 made of a first metal pattern 621a, and a second metal pattern 621b (see, e.g., Kim: fig. 1C, and par. [0030], [0050]). Lin, in a similar device to Kim, shows (see, e.g., Lin: fig. 8B) that the patterns 200 include a barrier layer pattern 212, a seed pattern 214, and a plating pattern 220 (see, e.g., Lin: par. [0017], and [0021]). Lin also shows that these patterns 200 are modifications and arrangements to form delamination-free structures (see, e.g., Lin: par. [0004] and [0029]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the patterns of Lin that include a barrier layer pattern, a seed pattern, and a plating pattern a in the device of Kim, in order to form delamination-free structures.
Kim in view of Lin shows (see, e.g., Lin: fig. 8B) that, viewed from a plan view, a sidewall of the barrier layer pattern 212 extends laterally beyond a sidewall of the seed layer pattern 214.
However, Kim in view of Lin fails (see, e.g., Kim: figs. 1B and annotated fig. 1B, and see, e.g., Lin: fig. 8B) to show that a thickness of the seed layer pattern 214 is within a range of 500 A to 1500 A. Ting, in a similar device to Kim in view of Lin, shows (see, e.g., Ting: fig. 4) that a thickness of the seed layer pattern (in the element 406) is within a range of 1000 A to 5000 A (a range of 100 nm to 500 nm) (see, e.g., Ting: par. [0089]). Ting also shows that the seed layer is deposited in order to form the redistribution wiring interconnects 406 (see, e.g., Ting: par. [0089]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the seed layer pattern of Ting in the device of Kim in view of Lin, in order to form the redistribution wiring interconnects.
However, the differences in the thicknesses of the seed layer pattern will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 13) of the mentioned thicknesses of the seed layer pattern, and Ting has identified such thicknesses of the seed layer pattern as result-effective variables subject to optimization (see, e.g., Ting: par. [0089]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Kim in view of Lin.
Regarding claim 12, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B and, and see, e.g., Lin: fig. 8B) that each of the first redistribution wirings 110/210 includes a recess configured by the sidewall of the seed layer pattern 214 recessed from a sidewall of the plating pattern 220 and the sidewall of the barrier layer pattern 212
Regarding claim 13, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the sidewall of the barrier layer pattern 212 and the sidewall of the4 plating pattern 220 are vertically aligned with each other.
Regarding claim 14, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the barrier layer pattern 212 has a first thickness, the seed layer pattern 214 has a second thickness, and the plating pattern 220 has a third thickness greater than the first thickness and greater than the second thickness.
Regarding claim 16, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that the each of the first redistribution wirings 110/210 includes a redistribution via V1/VH penetrating an underlying insulating layer 10/120, a redistribution pad L1 on the redistribution via V1/VH, and a redistribution line 110/210 extending from the redistribution pad L1 on the underlying insulating layer 10/120.
Regarding claim 18, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the barrier layer pattern 212 comprises titanium (see, e.g., Lin: par. [0017]), and the seed layer pattern 214 comprises copper (see, e.g., Lin: par. [0017]).
Regarding claim 19, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) that a second package PK2 on the upper redistribution wiring layer 2000, wherein the second package comprises a package substrate 810 and at least one second semiconductor chip 800 stacked on the package substrate 810.
Regarding claim 20, Kim shows (see, e.g., Kim: fig. 1B) most aspects of the instant invention including a semiconductor package 1, comprising:
A lower redistribution wiring layer 1000 having first redistribution wirings 110/210 stacked in at least two layers
A semiconductor chip 700 on the lower redistribution wiring layer 1000 and electrically connected to the first redistribution wirings 110/210
A sealing member 750 covering the semiconductor chip 700 on the lower redistribution wiring layer 1000
A plurality of through vias 930 penetrating the sealing member 750 and electrically connected to the first redistribution wirings 110/210
An upper redistribution wiring layer 2000 on the sealing member 750
Each of the first redistribution wirings 110/210 includes a redistribution via V1/VH penetrating an underlying insulating layer 10/120, a redistribution pad L1 on the redistribution via V1/VH, and a redistribution line 110/210 extending from the redistribution pad L1 on the underlying insulating layer 10/120
Each of the first redistribution wirings 110/210 includes patterns sequentially stacked
However, Kim fails (see, e.g., Kim: figs. 1B) to show that the patterns include a barrier layer pattern, a seed pattern, and a plating pattern. Kim shows that the patterns include similar layers as the barrier/seed layer 11, and the metal pattern 621 made of a first metal pattern 621a, and a second metal pattern 621b (see, e.g., Kim: fig. 1C, and par. [0030], [0050]). Lin, in a similar device to Kim, shows (see, e.g., Lin: fig. 8B) that the patterns 200 include a barrier layer pattern 212, a seed pattern 214, and a plating pattern 220 (see, e.g., Lin: par. [0017], and [0021]). Lin also shows that these patterns 200 are modifications and arrangements to form delamination-free structures (see, e.g., Lin: par. [0004] and [0029]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the patterns of Lin that include a barrier layer pattern, a seed pattern, and a plating pattern a in the device of Kim, in order to form delamination-free structures.
Kim in view of Lin shows (see, e.g., Lin: fig. 8B) that the redistribution line includes a recess configured by a sidewall of the seed layer pattern 214 recessed from a sidewall of the plating pattern 220 and a sidewall of the barrier layer pattern 212.
However, Kim in view of Lin fails (see, e.g., Kim: figs. 1B and annotated fig. 1B, and see, e.g., Lin: fig. 8B) to show that a thickness of the seed layer pattern 214 is within a range of 500 A to 1500 A. Ting, in a similar device to Kim in view of Lin, shows (see, e.g., Ting: fig. 4) that a thickness of the seed layer pattern (in the element 406) is within a range of 1000 A to 5000 A (a range of 100 nm to 500 nm) (see, e.g., Ting: par. [0089]). Ting also shows that the seed layer is deposited in order to form the redistribution wiring interconnects 406 (see, e.g., Ting: par. [0089]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the seed layer pattern of Ting in the device of Kim in view of Lin, in order to form the redistribution wiring interconnects.
However, the differences in the thicknesses of the seed layer pattern will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 13) of the mentioned thicknesses of the seed layer pattern, and Ting has identified such thicknesses of the seed layer pattern as result-effective variables subject to optimization (see, e.g., Ting: par. [0089]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Kim in view of Lin.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin in view of Ting in further view of Geissler (US 2018/0331053).
Regarding claims 5 and 15, Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) most aspects of the instant invention including a plating pattern 220.
However, Kim in view of Lin in view of Ting fails (see, e.g., Lin: fig. 8B) to show that the third thickness of the plating pattern is within a range of 2 µm to 10 µm. Kim in view of Lin in view of Ting shows (see, e.g., Lin: fig. 8B) that the third thickness of the plating pattern is greater than 25 µm (see, e.g., Lin: par. [0022]).
Geissler, in a similar device to Kim in view of Lin in view of Ting, shows (see, e.g., Geissler: fig. 8B) that the third thickness of the plating pattern (see, e.g., Geissler: par. [0027] and [0036], where the structured low-ohmic redistribution layer is equivalent to the layer 214) is more than 2 µm. Geissler also shows (see, e.g., Geissler: fig. 8B) that third thickness of the plating pattern more than 2 µm is to enable a structured low-ohmic redistribution layer (see, e.g., Geissler: par. [0027] and [0036]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the third thickness of the plating pattern of Geissler within a range of 2 µm to 10 µm in the device of Kim in view of Lin in view of Ting, in order to o enable a structured low-ohmic redistribution layer.
However, the differences in the thicknesses of the plating pattern will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 13) of the mentioned thicknesses of the plating pattern, and Geissler has identified such thicknesses of the plating pattern as result-effective variables subject to optimization (see, e.g., Geissler: par. [0027] and [0036]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Kim in view of Lin in view of Ting.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lin in view of Ting in further view of Yang (US 2022/0223548).
Regarding claims 7 and 17, Kim in view of Lin in view of Ting shows (see, e.g., Kim: fig. 1B) most aspects of the instant invention including a redistribution line.
However, Kim in view of Lin in view of Ting fails (see, e.g., Kim: fig. 1B) to show that the redistribution line has a width of 3 µm or less. Kim in view of Lin in view of Ting (see, e.g., Lin: fig. 8B) is silent about width of the redistribution. Yang, in a similar device to Kim in view of Lin in view of Ting, shows (see, e.g., Yang: figs. 11B and 13) that the width of the redistribution line is 3 µm or less (see, e.g., Yang: par. [0041], elements W1 and W2, where their difference can be a width range of less than or equal to 3 µm). Yang also shows that such a width of the redistribution line (of 3 µm or less) improves coplanarity of the conductive connectors, reduces the risk of cold joints, solder bridges, and the like, and reduces device defects and yield losses (see, e.g., Yang: par. [0040]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the width of the redistribution line is 3 µm or less of Yang in the device of Kim in view of Lin in view of Ting, in order to improve coplanarity of the conductive connectors, reduce the risk of cold joints, solder bridges, and the like, and reduce device defects and yield losses.
However, the differences in the widths of the redistribution line will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 13) of the mentioned widths of the redistribution line, and Yang has identified such widths of the redistribution line as result-effective variables subject to optimization (see, e.g., Yang: par. [0040]), it would have been obvious to one of ordinary skill in the art to use these width values in the device of Kim in view of Lin in view of Ting.
Response to Arguments
The examiner considered the Applicants’ arguments, but are moot in view of the new grounds of rejection.
The applicants argue:
Kim in view of Lin fails to show that a thickness of the seed layer pattern 214 is within a range of 500 A to 1500 A.
The examiner responds:
In view of the new grounds of rejection, Ting, however, teaches that (see, e.g., Ting: fig. 4) that a thickness of the seed layer pattern (in the element 406) is within a range of 1000 A to 5000 A (a range of 100 nm to 500 nm) (see, e.g., Ting: par. [0089]). Ting also shows that the seed layer is deposited in order to form the redistribution wiring interconnects 406 (see, e.g., Ting: par. [0089]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the seed layer pattern of Ting in the device of Kim in view of Lin, in order to form the redistribution wiring interconnects.
However, the differences in the thicknesses of the seed layer pattern will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned thicknesses of the seed layer pattern, and Ting has identified such thicknesses of the seed layer pattern as result-effective variables subject to optimization (see, e.g., Ting: par. [0089]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Kim in view of Lin.
Conclusion
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights