CTNF 18/235,062 CTNF 87109 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 – 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Terui et al. (JP 2016-021496A) . Regarding claim 1, in Figures 2 and 14, Terui discloses an interposer board comprising: a first insulating layer (top layer 15, Figure 2) having a first surface (top surface of layer 15) and a second surface (bottom surface of layer 15) facing each other; a first wiring layer (25B, 16A, 45B) buried in the first surface of the first insulating layer; a second insulating layer (second layer 15) disposed on the second surface of the first insulating layer; a cavity (30, Figure 2) disposed in a part of the first surface of the first insulating layer; and a first trench (32; recess 32, Figure 4) connected to the cavity along a first direction and disposed in the part of the first surface of the first insulating layer. Regarding claim 2, Terui discloses wherein: a depth of the cavity is substantially equal to a depth of the first trench (Figure 14). Regarding claim 3, Terui discloses a first solder resist layer located under the first surface of the first insulating layer, wherein the cavity and the first trench are disposed in the part of the first insulating layer and the first solder resist layer (Figure 14). Regarding claim 4, Terui discloses wherein: the depth of the cavity and the depth of the first trench are substantially equal to a sum of a thickness of the first wiring layer and a thickness of the first solder resist layer (Figure 14). Regarding claim 5, Terui discloses wherein: the cavity includes an additional cavity extending from the cavity, disposed in the first insulating layer, and having a width narrower than a width of the cavity, and the first trench includes an additional trench extending from the trench, disposed in the first insulating layer, and having a width narrower than a width of the first trench (Figure 14). Regarding claim 6, Terui discloses wherein: the depth of the cavity is substantially equal to a sum of a thickness of the first wiring layer, a thickness of the first solder resist layer, and a depth of the additional cavity, and the depth of the first trench is substantially equal to a sum of the thickness of the first wiring layer, the thickness of the first solder resist layer, and a depth of the additional trench (Figure 14). Regarding claim 7, Terui discloses wherein: a depth of the cavity is different from a depth of the first trench (Figure 14). Regarding claim 8, Terui discloses a first solder resist layer located under the first insulating layer, wherein the cavity is disposed in the part of the first insulating layer and the first solder resist layer, and the first trench is disposed in the first solder resist layer (Figure 14). Regarding claim 9, Terui discloses wherein: the depth of the cavity is substantially equal to a sum of a thickness of the first wiring layer and a thickness of the first solder resist layer, and the depth of the first trench is substantially equal to the thickness of the first solder resist layer (Figure 14). Regarding claim 10, Terui discloses wherein: the cavity includes an additional cavity extending from the cavity, disposed in the first insulating layer, and having a width narrower than a width of the cavity. Regarding claim 11, Terui discloses wherein: the depth of the cavity is substantially equal to a sum of the thickness of the first wiring layer, a thickness of the first solder resist layer, and a depth of the additional cavity, and the depth of the first trench is substantially equal to a sum of the thickness of the first wiring layer and the thickness of the first solder resist layer (Figure 14). Regarding claim 12, Terui discloses wherein: the first trench extends along the first direction, and the first trench includes a plurality of trenches located along a second direction different from the first direction (Figure 14). Regarding claim 13, Terui discloses a plurality of protrusions disposed in the cavity and extending from a bottom of the cavity (Figure 14). Regarding claim 14, Terui discloses a second trench connected to the cavity and disposed on a side of the cavity opposite to another side of the cavity where the first trench is disposed (Figure 14). Regarding claim 15, in Figures 2 and 14, Terui discloses a circuit board comprising: a first substrate (43, Figure 14); and an interposer board (10; wiring board 10 comprising insulating layers 15 and conductor layers 16, Figure 2) that is located on the first substrate (on bottom surface of layer 43, Figure 2), and includes a first insulating layer (top layer 15, Figure 2) having a first surface (top surface of layer 15) and a second surface (bottom surface of layer 15) facing each other, a first wiring layer (25B, 16A, 45B) buried in the first surface of the first insulating layer, a second insulating layer (second layer 15) located on the second surface of the first insulating layer, a cavity (30, Figure 2) disposed in a part of the first insulating layer, and a first trench (32; recess 32, Figure 4) connected to the cavity; an electronic component (30) disposed between the first substrate and the interposer board, and at least partially disposed in the cavity (Figure 14); and a molding layer (29F, Figure 14) located between the first substrate and the interposer board. Regarding claim 16, Terui discloses wherein: the interposer board further includes a first solder resist layer located under the first surface of the first insulating layer, and the cavity and the first trench are disposed in the part of the first insulating layer and the first solder resist layer (Figure 14). Regarding claim 17, Terui discloses wherein: the first trench extends along a first direction, and the first trench includes a plurality of trenches located along a second direction different from the first direction (Figure 14). Regarding claim 18, Terui discloses wherein: the interposer board further includes a first solder resist layer located under the first surface of the first insulating layer, the cavity is disposed in the part of the first insulating layer and the first solder resist layer, and the first trench is disposed in the first solder resist layer (Figure 14). Regarding claim 19, Terui discloses wherein: the cavity includes an additional cavity extending from the cavity, disposed in the first insulating layer, and having a width narrower than a width of the cavity, and the first trench includes an additional trench extended from the trench, disposed in the first insulating layer, and having a width narrower than a width of the first trench (Figure 14). Regarding claim 20, Terui discloses a plurality of protrusions disposed in the cavity and extending from a bottom of the cavity (Figure 14). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847 Application/Control Number: 18/235,062 Page 2 Art Unit: 2847 Application/Control Number: 18/235,062 Page 3 Art Unit: 2847 Application/Control Number: 18/235,062 Page 4 Art Unit: 2847 Application/Control Number: 18/235,062 Page 5 Art Unit: 2847 Application/Control Number: 18/235,062 Page 6 Art Unit: 2847 Application/Control Number: 18/235,062 Page 7 Art Unit: 2847