DETAILED ACTION
This Office Action is in response to Restriction/Elected, filed on 10/31/2025, on the application filed on 08/17/2023. Claims 1-16 and 19-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species 2. There being no allowable generic or linking claims. Election was made without traverse in the reply filed on 03/23/2021.
Additionally, since the Applicant elected Species 3 in the Election/Restriction filed on 10/31/2025, claim 18 will not be examined since the claim is dependent on base claim 17 that is given to Species 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 7, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (US20140240936A1 and Kobayashi hereinafter).
Regarding claim 1, Kobayashi discloses a system (item 70 of Fig. 6 and ¶[0066] shows and indicates system 70 {electronic device 70}), comprising: a multi-layer printed circuit board (PCB), including: a plurality of laminated layers, a plurality of electrical interconnect pads on an outer surface of the plurality of laminated layers, and a first plurality of magnetic material deposits on the outer surface of the plurality of laminated layers (items 300, 324, 321, 327, 326, 351, 310 of Fig. 6 and ¶[0076-0078] shows and indicates multi-layer printed circuit board (PCB) 300 {semiconductor package 300} that includes the plurality of laminated layers 324_321_327 {the following laminated layers: solder resist 324; board body 321; and solder resist 327}; the plurality of electrical interconnect pads 326 on the outer surface 310_351 {surface of wiring board 310 adjacent to the surface of magnetic thin film 351} of plurality of laminated layers 324_321_327, and first plurality of magnetic material deposits 351 {magnetic thin film 351} on the outer surface 310_351 of the plurality of laminated layers 324_321_327); and a device coupled to the PCB, wherein the device includes: an electronic component including a plurality of terminals, a base including a plurality of through-hole vias (items 200, 100, 110, 232, 222, 125, 121, 331 of Fig. 6 and ¶[0066-0070 & 0072-0076] shows and indicates device 200_100 {device formed by semiconductor package 200, indicated in ¶[0066 & 0073_0075-0076], and semiconductor package 100, indicated in ¶[0066-0067_0070 & 0072-0073]} coupled to the PCB 300; where device 200_100 includes electronic component 232 {semiconductor device 232, indicated in ¶[0074]} including the plurality of terminals 222 {mounting pads 222, indicated in ¶[0074]}; and where device 200_100 includes base 110 {wiring board 110, indicated in ¶[0067_0070 & 0072-0073]} including the plurality of through-hole vias {since the wiring patterns 125 are electrically connected to the wiring patterns on the upper face of the board body 121 by way of via holes which are not shown, indicated in ¶[0069], and electronic component 331 is connected to the semiconductor device 232 of the semiconductor package 200 by way of via holes which not shown, indicated in ¶[0076], then base/wiring board 110 will have a plurality of through-hole vias}), wherein each through-hole via of the plurality of through-hole vias is electrically connected to a terminal of the plurality of terminals (Fig. 6 and ¶[0069_0074 & 0076] is extrapolated to indicate where each through-hole via of the plurality of through-hole vias is electrically connected to terminal 222 of the plurality of terminals 222 {electrical connection is established through the following: through via holes [not shown] in board body 121 that are electrically connecting to pads 123; where pads 123 are electrically connecting to solder balls 71; where solder balls 71 are electrically connecting to pads 226; and where pads 226 are electrically connecting to terminals 222 through via holes [not shown] in board body 210}), wherein the electronic component is mounted to the first surface of the base (items 124, 151 of Fig. 6 and ¶[0067-0068 & 0072] shows and indicates where electronic component 232 is mounted to the first surface 124_151 {surface of solder resist 124 adjacent to the surface of magnetic thin film 151} of base 110), and a second plurality of magnetic material deposits on a second surface of the base, wherein the second surface is opposite the first surface (items 151, 127 of Fig. 6 and ¶[0067-0068 & 0072] shows and indicates a second plurality of magnetic material deposits 151 {magnetic thin film 151} on the second surface 127_151 {surface of solder resist 127 adjacent to the surface of magnetic thin film 151} of base 110; where the second surface 127_151 is opposite the first surface 124_151), wherein when the device is coupled to the PCB, each magnetic material deposit of the first plurality of magnetic material deposits is attracted by a magnetic force to the magnetic material deposit of the second plurality of magnetic deposits and each through-hole via of the plurality of through-hole vias is electrically connected to an electrical interconnect pad of the plurality of electrical interconnect pads (items 72, 223 of Fig. 6 and ¶[0066-0069_0072-0076 & 0078] is interpreted to show and indicate where when device 200_100 is coupled to PCB 300, then each magnetic material deposit of first plurality of magnetic material deposits 351 is attracted by the magnetic force to the magnetic material deposit of second plurality of magnetic material deposits 151, and where each through-hole via of the plurality of through-hole vias is electrically connected to electrical interconnect pad 326 of the plurality of electrical interconnect pads 326 {electrical connection is established through the following: through solder balls 72 electrically connecting to pads 223; pads 223 electrically connecting to via holes [not shown] in board body 221; and via holes in board body 221 electrically connecting to terminals 222}), wherein at least one of the magnetic material deposits of the first plurality of magnetic material deposits and the magnetic material deposits of the second plurality of magnetic material deposits includes a permanent magnetic material (Fig. 6 and ¶[0066-0069_0072-0076 & 0078] shows and indicates where the magnetic material deposits of first plurality of magnetic material deposits 351 and the magnetic material deposits of second plurality of magnetic material deposits 151 includes permanent magnetic material { Ni—Zn ferrite}).
Regarding claim 6, Kobayashi discloses a system, wherein the electronic component includes a semiconductor integrated circuit and the device includes a semiconductor package (item 12a to 12c of Fig. 1a & Fig. 6 and ¶[0014 & 0066-0067 & 0072-0076] shows and indicates where electronic component 232 includes a semiconductor integrated circuit {since electronic components 12a to 12c are semiconductor integrated circuits [LSI], then it is interpreted that semiconductor device 232 is a semiconductor integrated circuit} and device 200_100 includes a semiconductor package).
Regarding claim 7, Kobayashi discloses a system, wherein the first plurality of magnetic material deposits include Nickel, Iron, Cobalt, samarium Cobalt, and/or rare-earth materials such as neodymium (Fig. 6 and ¶[0078] shows and indicates where first plurality of magnetic material deposits 351 include Nickel {Ni—Zn ferrite}).
Regarding claim 8, Kobayashi discloses a system, wherein at least one of the magnetic material deposits of the first plurality of magnetic material deposits surrounds at least one electrical interconnect pad of the plurality of electrical interconnect pads (Fig. 6 and ¶[0077-0078] shows where magnetic material deposits of first plurality of magnetic material deposits 351 surrounds electrical interconnect pad 326 of the plurality of electrical interconnect pads 326).
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weis et al. (US20200119490A1 and Weis hereinafter, cited in the 01/18/2025 IDS and the 01/25/2025 European Search Opinion).
Regarding claim 1, Weis discloses a system (item 100 of Fig. 8 and ¶[0088] shows and indicates system 100 {electric devices 100}), comprising: a multi-layer printed circuit board (PCB), including: a plurality of laminated layers, a plurality of electrical interconnect pads on an outer surface of the plurality of laminated layers, and a first plurality of magnetic material deposits on the outer surface of the plurality of laminated layers (items 102, 176, 114, 104 of Fig. 8 and ¶[0045_0066_0089-0090] shows and indicates multi-layer printed circuit board (PCB) 102 { first component carrier structure 102} that includes the plurality of laminated layers 102-carrier-layers {component carrier is a laminate-type component carrier, indicated in ¶[0045]}; the plurality of electrical interconnect pads 176-bottom {bottom solder structures 176} on the outer surface 114-surface-102 {surface of the electrically insulating layer structures 114 in the first component carrier structure 102} of plurality of laminated layers 102-carrier-layers, and first plurality of magnetic material deposits 104 {first magnet structure 104} on the outer surface 114-surface-102 of the plurality of laminated layers 102-carrier-layers); and a device coupled to the PCB, wherein the device includes: an electronic component including a plurality of terminals, a base including a plurality of through-hole vias (items 108, 102, 114, 116, 120, 176, 150 of Fig. 8 and ¶[0066 & 0089-0090] shows and indicates device 108 {second component carrier structure 108} coupled to the PCB 102; where device 108 includes electronic component 120-top {top surface mounted components 120} including the plurality of terminals 176-top {top solder structures 176}; and where device 108 includes base 114-top {top electrically insulating layer structures 114} including the plurality of through-hole vias 116-top {top conductive layer structures 116 of the stack 150}), wherein each through-hole via of the plurality of through-hole vias is electrically connected to a terminal of the plurality of terminals (Fig. 8 and ¶[0089-0090] shows and indicates where each through-hole via 116-top of the plurality of through-hole vias 116-top is electrically connected to terminal 176-top of the plurality of terminals 176-top), wherein the electronic component is mounted to the first surface of the base (Fig. 8 and ¶[0066 & 0089-0090] shows and indicates where electronic component 120-top is mounted to the first surface 114-top-surface-108 {top surface of electrically insulating layer structures 114 within second component carrier structure 108} of base 114-top), and a second plurality of magnetic material deposits on a second surface of the base, wherein the second surface is opposite the first surface (item 110 of Fig. 8 and ¶[0066 & 0089-0090] shows and indicates a second plurality of magnetic material deposits 110 {second magnet structure 110} on the second surface 114-bottom-surface-108 {bottom surface of electrically insulating layer structures 114 within second component carrier structure 108} of base 114-top; where the second surface 114-bottom-surface-108 is opposite the first surface 114-top-surface-108), wherein when the device is coupled to the PCB, each magnetic material deposit of the first plurality of magnetic material deposits is attracted by a magnetic force to the magnetic material deposit of the second plurality of magnetic deposits and each through-hole via of the plurality of through-hole vias is electrically connected to an electrical interconnect pad of the plurality of electrical interconnect pads (Fig. 8 and ¶[0089-0090] shows and indicates where when device 108 is coupled to PCB 102, then each magnetic material deposit of first plurality of magnetic material deposits 104 is attracted by the magnetic force to the magnetic material deposit of second plurality of magnetic material deposits 110, and where each through-hole via 116-top of the plurality of through-hole vias 116-top is electrically connected to electrical interconnect pad 176-bottom of the plurality of electrical interconnect pads 176-bottom), wherein at least one of the magnetic material deposits of the first plurality of magnetic material deposits and the magnetic material deposits of the second plurality of magnetic material deposits includes a permanent magnetic material (Fig. 8 and ¶[0089-0090] shows and indicates where the magnetic material deposits of first plurality of magnetic material deposits 104 and the magnetic material deposits of second plurality of magnetic material deposits 110 includes permanent magnetic material).
Claims 9, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi.
Regarding claim 9, Kobayashi discloses a device (items 200, 100 of Fig. 6 and ¶[0066-0067 & 0072-0073_0075-0076] shows and indicates device 200_100 {device formed by semiconductor package 200, indicated in ¶[0066 & 0073_0075-0076], and semiconductor package 100, indicated in ¶[0066-0067 & 0072-0073]}), comprising: an electronic component including a plurality of terminals (items 232, 222 of Fig. 6 and ¶[0074] shows and indicates electronic component 232 {semiconductor device 232} that includes the plurality of terminals 222 {mounting pads 222}), a base including a plurality of through-hole vias (item 110 of Fig. 6 and ¶[ 0067_0069-0070_0072-0073 & 0076] shows and indicates base 110 {wiring board 110, indicated in ¶[0067_0070 & 0072-0073]} including the plurality of through-hole vias {since the wiring patterns 125 are electrically connected to the wiring patterns on the upper face of the board body 121 by way of via holes which are not shown, indicated in ¶[0069], and electronic component 331 is connected to the semiconductor device 232 of the semiconductor package 200 by way of via holes which not shown, indicated in ¶[0076], then base/wiring board 110 will have a plurality of through-hole vias}), wherein each through-hole via of the plurality of through-hole vias is electrically connected to a terminal of the plurality of terminals (Fig. 6 and ¶[0069_0074 & 0076] is extrapolated to indicate where each through-hole via of the plurality of through-hole vias is electrically connected to terminal 222 of the plurality of terminals 222 {electrical connection is established through the following: through via holes [not shown] in board body 121 that are electrically connecting to pads 123; where pads 123 are electrically connecting to solder balls 71; where solder balls 71 are electrically connecting to pads 226; and where pads 226 are electrically connecting to terminals 222 through via holes [not shown] in board body 210}), wherein the electronic component is mounted to a first surface of the base (items 124, 151 of Fig. 6 and ¶[0067-0068 & 0072] shows and indicates where electronic component 232 is mounted to the first surface 124_151 {surface of solder resist 124 adjacent to the surface of magnetic thin film 151} of base 110), and a first plurality of magnetic material deposits on a second surface of the base, wherein the second surface is opposite the first surface (items 151, 127 of Fig. 6 and ¶[0067-0068 & 0072] shows and indicates a first plurality of magnetic material deposits 151 {magnetic thin film 151} on the second surface 127_151 {surface of solder resist 127 adjacent to the surface of magnetic thin film 151} of base 110; where the second surface 127_151 is opposite the first surface 124_151), wherein the device is configured to couple to a substrate, wherein: the substrate includes a plurality of electrical interconnect pads on an outer surface of the substrate (items 300, 326 of Fig. 6 and ¶[0076-0078] shows and indicates where device 200_100 is configured to couple to substrate 300 {semiconductor package 300}; and where substrate 300 includes the plurality of electrical interconnect pads 326 on the outer surface 310_351 {surface of wiring board 310 adjacent to the surface of magnetic thin film 351} of substrate 300), and a second plurality of magnetic material deposits on the outer surface of the substrate (item 351 of Fig. 6 and ¶[0078] shows and indicates second plurality of magnetic material deposits 351 {magnetic thin film 351} on the outer surface 310_351 of substrate 300), when the device is coupled to the substrate, each magnetic material deposit of the first plurality of magnetic material deposits is attracted by a magnetic force to a magnetic material deposit of the second plurality of magnetic deposits and each through-hole via of the plurality of through-hole vias is electrically connected to an electrical interconnect pad of the plurality of electrical interconnect pads (items 72, 223 of Fig. 6 and ¶[0066-0069_0072-0076 & 0078] is interpreted to show and indicate where when device 200_100 is coupled to substrate 300, then each magnetic material deposit of first plurality of magnetic material deposits 151 is attracted by the magnetic force to the magnetic material deposit of second plurality of magnetic material deposits 351, and where each through-hole via of the plurality of through-hole vias is electrically connected to electrical interconnect pad 326 of the plurality of electrical interconnect pads 326 {electrical connection is established through the following: through solder balls 72 electrically connecting to pads 223; pads 223 electrically connecting to via holes [not shown] in board body 221; and via holes in board body 221 electrically connecting to terminals 222}), and at least one of the magnetic material deposits of the first plurality of magnetic material deposits and the magnetic material deposits of the second plurality of magnetic material deposits includes a permanent magnetic material (Fig. 6 and ¶[0066-0069_0072-0076 & 0078] shows and indicates the magnetic material deposits of first plurality of magnetic material deposits 151 and the magnetic material deposits of second plurality of magnetic material deposits 351 includes permanent magnetic material { Ni—Zn ferrite}).
Regarding claim 14, Kobayashi discloses a device, wherein the electronic component includes a semiconductor integrated circuit and the device includes a semiconductor package (item 12a to 12c of Fig. 1a & Fig. 6 and ¶[0014 & 0066-0067 & 0072-0076] shows and indicates where electronic component 232 includes a semiconductor integrated circuit {since electronic components 12a to 12c are semiconductor integrated circuits [LSI], then it is interpreted that semiconductor device 232 is a semiconductor integrated circuit} and device 200_100 includes a semiconductor package).
Regarding claim 15, Kobayashi discloses a device, wherein the first plurality of magnetic material deposits include Nickel, Iron, Cobalt, samarium Cobalt, and/or rare-earth materials such as neodymium (Fig. 6 and ¶[0072] shows and indicates where first plurality of magnetic material deposits 151 include Nickel {Ni—Zn ferrite}).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi, as detailed in the rejection of claim 9 above, in view of Cordes et al. (US20020113324Al and Cordes hereinafter).
Regarding claim 10, Kobayashi discloses a device, wherein each through-hole via of the plurality of through-hole vias (Fig. 6 and ¶[0069 & 0076] indicates where through-hole via of the plurality of through-hole vias {base/wiring board 110 will have a plurality of through-hole vias, as indicated in ¶[0069 & 0076]}).
However, Kobayashi does not disclose wherein each through-hole via includes a solder material.
Cordes disclose wherein each through-hole via includes a solder material (¶[0064] and indicates where each through-hole via of the plurality of through-hole vias includes a solder material {solder will enter and fill via holes}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein each through-hole via includes a solder material into the structure of Kobayashi. One would have been motivated in the device of Kobayashi and have the through-hole via include a solder material, in order to fill the conductive substrate features that are larger than 6 microns with solder, as indicated by Cordes in ¶[0064], in the device of Kobayashi.
Regarding claim 11, modified Kobayashi discloses a device, wherein the solder material of a first through-hole via of the plurality of through-hole vias has a thickness of at least 1 micron (Kobayashi: Fig. 6 and ¶[0069 & 0076] indicates where through-hole via of the plurality of through-hole vias {base/wiring board 110 will have a plurality of through-hole vias, as indicated in ¶[0069 & 0076]}; Cortes: ¶[0064] indicates through-hole via has a thickness of at least 1 micron {through-hole via filled that are larger than 6 microns}).
Claim 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weis.
Regarding claim 9, Weis discloses a device (item 108 of Fig. 8 and ¶[0089-0090] shows and indicates device 108 {second component carrier structure 108}), comprising: an electronic component including a plurality of terminals (items 120, 176 of Fig. 8 and ¶[0089-0090] shows and indicates electronic component 120-top {top surface mounted components 120} including the plurality of terminals 176-top {top solder structures 176}), a base including a plurality of through-hole vias (items 114, 116, 150 of Fig. 8 and ¶[0066 & 0089-0090] shows and indicates base 114-top {top electrically insulating layer structures 114} including the plurality of through-hole vias 116-top {top conductive layer structures 116 of the stack 150}), wherein each through-hole via of the plurality of through-hole vias is electrically connected to a terminal of the plurality of terminals (Fig. 8 and ¶[0089-0090] shows and indicates where each through-hole via 116-top of the plurality of through-hole vias 116-top is electrically connected to terminal 176-top of the plurality of terminals 176-top), wherein the electronic component is mounted to a first surface of the base (Fig. 8 and ¶[0066 & 0089-0090] shows and indicates where electronic component 120-top is mounted to the first surface 114-top-surface-108 {top surface of electrically insulating layer structures 114 within second component carrier structure 108} of base 114-top), and a first plurality of magnetic material deposits on a second surface of the base, wherein the second surface is opposite the first surface (item 110 of Fig. 8 and ¶[0066 & 0089-0090] shows and indicates a first plurality of magnetic material deposits 110 {second magnet structure 110} on the second surface 114-bottom-surface-108 {bottom surface of electrically insulating layer structures 114 within second component carrier structure 108} of base 114-top; where the second surface 114-bottom-surface-108 is opposite the first surface 114-top-surface-108), wherein the device is configured to couple to a substrate, wherein: the substrate includes a plurality of electrical interconnect pads on an outer surface of the substrate (items 102, 176 of Fig. 8 and ¶[0045 & 0089] shows and indicates where device 108 is configured to couple to substrate 102 {first component carrier structure 102}; and where substrate 102 includes the plurality of electrical interconnect pads 176-bottom {bottom solder structures 176} on the outer surface 114-surface-102 {surface of the electrically insulating layer structures 114 in the first component carrier structure 102} of substrate 102), and a second plurality of magnetic material deposits on the outer surface of the substrate (item 104 of Fig. 8 and ¶[0089] shows and indicates second plurality of magnetic material deposits 104 {first magnet structure 104} on the outer surface 114-surface-102 of substrate 102), when the device is coupled to the substrate, each magnetic material deposit of the first plurality of magnetic material deposits is attracted by a magnetic force to a magnetic material deposit of the second plurality of magnetic deposits and each through-hole via of the plurality of through-hole vias is electrically connected to an electrical interconnect pad of the plurality of electrical interconnect pads (Fig. 8 and ¶[0089-0090] shows and indicates where when device 108 is coupled to substrate 102, then each magnetic material deposit of first plurality of magnetic material deposits 110 is attracted by the magnetic force to the magnetic material deposit of second plurality of magnetic material deposits 104, and where each through-hole via 116-top of the plurality of through-hole vias 116-top is electrically connected to electrical interconnect pad 176-bottom of the plurality of electrical interconnect pads 176-bottom), and at least one of the magnetic material deposits of the first plurality of magnetic material deposits and the magnetic material deposits of the second plurality of magnetic material deposits includes a permanent magnetic material (Fig. 8 and ¶[0089-0090] shows and indicates where the magnetic material deposits of first plurality of magnetic material deposits 110 and the magnetic material deposits of second plurality of magnetic material deposits 104 includes permanent magnetic material).
Claims 16, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi.
Regarding claim 16, Kobayashi discloses a device (items 200, 100 of Fig. 6 and ¶[0066-0067 & 0072-0073_0075-0076] shows and indicates device 200_100 {device formed by semiconductor package 200, indicated in ¶[0066 & 0073_0075-0076], and semiconductor package 100, indicated in ¶[0066-0067 & 0072-0073]}), comprising: a substrate (item 300 of Fig. 6 and ¶[0076 & 0078] shows and indicates substrate 300 {semiconductor package 300}), including: a plurality of laminated layers (items 324, 321, 327 of Fig. 6 and ¶[0076-0077] shows and indicates the plurality of laminated layers 324_321_327 {the following laminated layers: solder resist 324; board body 321; and solder resist 327}), a plurality of electrical interconnect pads on an outer surface of the plurality of laminated layers (items 326, 351, 310 of Fig. 6 and ¶[0076-0078] shows and indicates the plurality of electrical interconnect pads 326 on the outer surface 310_351 {surface of wiring board 310 adjacent to the surface of magnetic thin film 351} of plurality of laminated layers 324_321_327), and a first plurality of magnetic material deposits on the outer surface of the plurality of laminated layers (item 351, 310 of Fig. 6 and ¶[0078] shows and indicates first plurality of magnetic material deposits 351 {magnetic thin film 351} on the outer surface 310_351 of the plurality of laminated layers 324_321_327).
Regarding claim 19, Kobayashi discloses a device, wherein the first plurality of magnetic material deposits include Nickel, Iron, Cobalt, samarium Cobalt, and/or rare-earth materials such as neodymium (Fig. 6 and ¶[0078] shows and indicates where first plurality of magnetic material deposits 351 include Nickel {Ni—Zn ferrite}).
Regarding claim 20, Kobayashi discloses a device, wherein at least one of the magnetic material deposits of the first plurality of magnetic material deposits surrounds at least one electrical interconnect pad of the plurality of electrical interconnect pads (Fig. 6 and ¶[0077-0078] shows where magnetic material deposits of first plurality of magnetic material deposits 351 surrounds electrical interconnect pad 326 of the plurality of electrical interconnect pads 326).
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weis.
Regarding claim 16, Weis discloses a device (item 108 of Fig. 8 and ¶[0089-0090] shows and indicates device 108 {second component carrier structure 108}), comprising: a substrate (item 102 of Fig. 8 and ¶[0045 & 0089] shows and indicates substrate 102 {first component carrier structure 102}), including: a plurality of laminated layers (Fig. 8 and ¶[0045_0066_0089-0090] shows and indicates plurality of laminated layers 102-carrier-layers {component carrier is a laminate-type component carrier, indicated in ¶[0045]), a plurality of electrical interconnect pads on an outer surface of the plurality of laminated layers (items 102, 176, 114, 104 of Fig. 8 and ¶[0045_0066_0089-0090] shows and indicates the plurality of plurality of electrical interconnect pads 176-bottom {bottom solder structures 176} on the outer surface 114-surface-102 {surface of the electrically insulating layer structures 114 in the first component carrier structure 102} of the plurality of laminated layers 102-carrier-layers), and a first plurality of magnetic material deposits on the outer surface of the plurality of laminated layers (item 110 of Fig. 8 and ¶[0066 & 0089-0090] shows and indicates a first plurality of magnetic material deposits 110 {second magnet structure 110} on the outer surface 114-surface-102 of the plurality of laminated layers 102-carrier-layers).
Allowable Subject Matter
Claims 2-5 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the primary reason for allowance is due to a system, wherein each through-hole via of the plurality of through-hole vias includes a solder material and wherein when the device is coupled to the PCB the magnetic force causes at least a portion of the solder material to deform.
Regarding claims 3-4, the primary reason for allowance is due to the dependency on claim 2.
Regarding claim 5, the primary reason for allowance is due to a system, wherein the plurality of through-hole vias include conductive materials having a Rockwell hardness number of 16 HB or less.
Regarding claim 12, the primary reason for allowance is due to a device, wherein an outer coating of solder of the first through-hole via protrudes beyond the second surface of the base.
Regarding claim 13, the primary reason for allowance is due to a device, wherein the plurality of through-hole vias include conductive materials having a Rockwell hardness number of 16 HB or less.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847