Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claim 1-10 in the reply filed on 5/15/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7,10 and 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (20210257325).
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Regarding claim 1, Chung teaches an semiconductor package (fig. 20) comprising:
a package substrate (fig. 17: 100b) including:
a ball pad including first (please see multiple portions of 170+172 in fig. 12, specifically the portions in openings 142 and 144) and second (please see multiple portions of 170+172 in fig. 12) pads on a lower surface of the package substrate,
a wiring line (fig. 17: 130) extending between the first pad and the second pad on the lower surface (please see fig. 20 which shows 100b at the bottom of the total package), and
a solder mask layer (fig. 17: 140a + 148; please note that 140a and 148 function as a solder mask, being placed atop of wiring and protecting wiring, as well as controlling where the solder flows) covering the wiring line and the ball pad (please see 140a and 148 covering multiple surfaces of multiple portions of 170+172 and 130),
wherein the solder mask layer includes a first opening (fig. 11: 142) exposing a portion of the first pad and a second opening (fig. 11: 144) exposing a portion of the second pad (please see fig. 17 which shows 140a and 148 covering portions of 170+172, leaving the rest of 170+172 exposed);
a semiconductor chip (fig. 20: 420) on an upper surface of the package substrate; and
a connection bump (fig. 17: 150b+160b; please note that in the art, it is commonly understood that a solder bump structure includes the UBM and solder bump, the UBM acting as the part of the solder bump structure that ensures a strong, stable connection between the bump and the pad) on a lower surface of the ball pad and connected to the first and second pads (please see fig. 17),
wherein the connection bump covers a lower surface and a first side surface of the first pad exposed through the first opening (please see160b and 150b covering multiple sides of 170+172), a lower surface and side surfaces of a region of the solder mask layer covering the wiring line (please see160b and 150b covering multiple sides of 170+172), and a lower surface and a first side surface of the second pad exposed through the second opening (please see160b and 150b covering multiple sides of 170+172).
Please note that intended use was utilized in the rejection above, namely for the solder mask. It would have been obvious to a PHOSITA, at the time of filing, to know that 140+148 is being used as a solder mask since it is being used in the same manner and has the same function.
Further, multiple embodiments are used, like fig. 10, because this view shows the to down view.
Regarding claim 2, Chung teaches an semiconductor package of claim 1, wherein the connection bump covers side surfaces of the solder mask layer defining the first and second openings (please see fig. 17, which shows 160b and 150b covering almost the entirety of 140+148).
Regarding claim 3, Chung teaches an semiconductor package of claim 1, wherein the first side surfaces of the first and second pads are side surfaces facing the wiring line (please see fig. 17).
Regarding claim 4, Chung teaches an semiconductor package of claim 1, wherein the package substrate further includes insulating layers and redistribution layers that are vertically and alternately stacked on each other, wherein the connection bump contacts a first portion and a second portion of a lowermost insulating layer, among the insulating layers, and wherein the first portion of the lowermost insulating layer is exposed between the wiring line and the first side surface of the first pad, and the second portion of the lowermost insulating layer is exposed between the wiring line and the first side surface of the second pad (please see fig. 20).
Regarding claim 5, Chung teaches an semiconductor package of claim 1, wherein the wiring line is a ground line, and at least one of the first and second pads are electrically connected to a first signal line (as seen in fig. 17 and 20, 130 functions as an RDL, being connected to all lines, and by extension 170+172 is also connected to these lines by being connected to 130).
Regarding claim 6, Chung teaches an semiconductor package of claim 5, wherein the package substrate further includes insulating layers and redistribution layers that are alternately and vertically stacked on each other, wherein the redistribution layers include a first redistribution layer that is adjacent to and perpendicularly overlaps the wiring line, and wherein the first redistribution layer is configured to form a second signal line (as seen in fig. 17 and 20, 130 functions as an RDL, being connected to all lines, and by extension 170+172 is also connected to these lines by being connected to 130).
Regarding claim 7, Chung teaches an semiconductor package of claim 1, wherein the package substrate further includes: insulating layers and redistribution layers that are alternately and vertically stacked on each other, and redistribution vias connected to the redistribution layers, and wherein at least one of the first and second pads is connected to at least one of the redistribution vias (please see fig. 17 and 20).
Regarding claim 10, Chung teaches an semiconductor package of claim 1, wherein the first and second pads are symmetrically disposed on opposite sides of the wiring line, and wherein the connection bump has a symmetrical shape with respect to the wiring line (please see fig. 10 which shows concentric nature of the structures).
Regarding claim 12, Chung teaches an semiconductor package of claim 1, wherein the first pad has a shape corresponding to a first portion of a circle, wherein the second pad has a shape corresponding to a second portion of the circle (please see fig. 10 which shows concentric nature of the structures),
wherein the ball pad further includes a third pad having a shape corresponding to a third portion of the circle (please see fig. 10 which shows concentric nature of the structures), and
wherein the wiring line extends between the first and third pads or between the second and third pads (please see fig. 10 which shows concentric nature of the structures).
Regarding claim 13, Chung teaches an semiconductor package of claim 1, wherein the package substrate further includes a lower via arranged to be connected to the wiring line on the lower surface of the package substrate (please see fig. 17 and 20).
Regarding claim 14, Chung teaches an semiconductor package comprising:
a package substrate (fig. 17: 100b) including:
a first ball pad including a first pad (please see multiple portions of 170+172 in fig. 12, specifically the portions in openings 142 and 144) and a second pad (please see multiple portions of 170+172 in fig. 12, specifically the portions in openings 142 and 144) that are disposed on a lower surface of the package substrate,
a second ball pad including a third pad having a first shape and disposed on the lower surface of the package substrate (please see multiple portions of 170+172 in fig. 12, specifically the portions in openings 142 and 144),
a wiring line (fig. 17: 130) extending between the first pad and the second pad on the lower surface, and a solder mask layer covering the wiring line and the first ball pad,
wherein the solder mask layer includes a first opening (fig. 11: 142) exposing a portion of the first pad and a second opening (fig. 11: 144) exposing a portion of the second pad; and
a connection bump (fig. 17: 150b+160b; please note that in the art, it is commonly understood that a solder bump structure includes the UBM and solder bump, the UBM acting as the part of the solder bump structure that ensures a strong, stable connection between the bump and the pad) on a lower surface of the first ball pad and connected to the first and second pads,
wherein the first pad has a shape corresponding to a first portion of the first shape of the third pad in a plan view, wherein the second pad has a shape corresponding to a second portion of the first shape of the third pad in a plan view (please see fig. 10), and
wherein the connection bump contacts a portion of a lower surface and a side surface of each of the first and second pads (please see160b and 150b covering multiple sides of 170+172).
Please note that intended use was utilized in the rejection above, namely for the solder mask. It would have been obvious to a PHOSITA, at the time of filing, to know that 140+148 is being used as a solder mask since it is being used in the same manner and has the same function.
Further, multiple embodiments are used, like fig. 10, because this view shows the to down view.
Regarding claim 15, Chung teaches an semiconductor package of claim 14, wherein an upper end of the connection bump is located at a level higher than a level of the lower surface of each of the first and second pads (please see fig. 17 and 20).
Regarding claim 16, Chung teaches an semiconductor package of claim 14, wherein an uppermost surface of the connection bump is substantially coplanar with upper surfaces of the first and second pads (please see fig. 17 and 20).
Regarding claim 17, Chung teaches an semiconductor package of claim 14, wherein the second ball pad is spaced apart from the first ball pad, and wherein the first shape of the second ball pad is a circle (please see fig. 10, 17 and 20).
Regarding claim 18, Chung teaches an semiconductor package of claim 14, wherein the package substrate further includes a third ball pad spaced apart from each of the first ball pad and the second ball pad, and wherein the third ball pad includes a fourth pad having a shape corresponding to a portion of the first shape of the third pad of the second ball pad ((please see fig. 10, 17 and 20).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 allowed.
The following is an examiner’s statement of reasons for allowance: prior art, alone or in combination fails to teach all the limitations mentioned in claim 19, such as “wherein the first ball pad has a shape different from a shape of the second ball pad”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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