DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed February 2nd, 2026 are noted. Applicant did not amend the Specification to overcome the objections set forth in the Non-Final Office Action mailed 11/25/2025, so the objection(s) to the Title remains.
Applicant’s amendments to the claims are noted.
3. Claims 9, 12, 16-18, 22-24, 27, and 29 are now canceled; Claims 1-8, 10-11, 13-15, 19-21, 25-26, 28, and 30 remain pending in the application.
4. Claims 1-8, 10-11, 13-15, 19-21, 25-26, 28, and 30 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION LAYER HAVING THROUGH HOLE”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-11, 13-15, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PG Pub No US2018/0076156A1) (of record).
Regarding claim 1, Kim teaches a semiconductor package (100E) fig. 15 [0115], comprising (refer to annotated fig. 15 below):
an interposer substrate (comprising 150 with 160) [0066];
a chip stack (stack of 125’s) [0115] on (supported by bottom of) the interposer substrate (comprising 150 with 160) and including a plurality of first semiconductor chips (memory chips 125s) [0115] that are vertically stacked;
a second semiconductor chip (120) [0115] (processor/logic chip 120) [0032, 0078, 0115] on (supported by bottom of) the interposer substrate (comprising 150 with 160) and horizontally spaced apart from the chip stack (125s);
a molding layer (130) [0113] disposed on (supported by bottom of) the interposer substrate (comprising 150 with 160) and surrounding a side surface of each of the chip stack (125s) and the second semiconductor chip (120);
a redistribution layer (141 hosting collective 112, 142 redistribution material) [0066, 0083, 0113] on the molding layer (130); and
a plurality of conductive posts (113 a-b posts) [0087-0088] that vertically penetrate the molding layer (130) and electrically connect the interposer substrate (comprising 160 in 150) [0066] to the redistribution layer (141 hosting collective 112, 142 redistribution material) [0066, 0083, 0113] (160, 142 with 112, and 113 are mutually-interconnected conductive layers [0091, 0075, 0085, 0115]).
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Annotated fig. 15 of Kim showing flipped perspective package considered from
Regarding claim 2, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches wherein:
the redistribution layer (comprising 142 redistribution material) [0066, 0113] has a through hole (110Ha) [0015] that vertically (partially) penetrates the redistribution layer (collective 142 material), and the through hole (110Ha) is (partially) above the second semiconductor chip (120) [0115] (in flipped perspective of fig. 15 – see above).
Regarding claim 3, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 2. Kim also teaches further comprising a first dummy chip (111a) [0115] in the through hole (110Ha) [0015].
Regarding claim 4, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 2. Kim also teaches wherein the first dummy chip (111a) [0115] contacts a top surface of the second semiconductor chip (through corresponding electrically-connected 142/143 material [0088-0089, 0115]).
Regarding claim 5, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 2. Kim also teaches a top surface of the second semiconductor chip (120) [0115] is coplanar (tops overlap in same vertical plane) with a top surface of the molding layer (130) [0115], and the through hole (110Ha with 141 hole(s)) [0115] exposes the top surface of the second semiconductor chip (120) (in flipped perspective of annotated fig. 15 above).
Regarding claim 6, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 2. Kim also teaches wherein:
a top (topmost) surface of the second semiconductor chip (120) [0115] is at a level lower than a level of a top (topmost) surface of the molding layer (130) [0115] (see flipped perspective annotated fig. 15 above), and
the through hole (110Ha with attached 141 hole(s)) [0115] penetrates the redistribution layer (comprising 142 material) and an upper portion of the molding layer (130) and exposes the top surface of the second semiconductor chip (120).
Regarding claim 7, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 2. Kim also teaches further comprising:
a thermal radiation member (metal members 122/129) [0078, 0155] on a top surface of the second semiconductor chip (120) [0115], wherein the top surface of the second semiconductor chip (120) is at a level lower than a level of a top surface of the molding layer (130) [0115], and wherein the through hole (110Ha with attached 141 hole(s)) [0115] exposes a top surface of the thermal radiation member (122/129 metal member) (in flipped perspective of fig. 15).
Regarding claim 8, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches wherein each of the plurality of conductive posts includes (is included with):
a lower post (113b) [0115] (thermally/electrically) connected to the interposer substrate (comprising 150 with 160) [0066] (see flipped perspective in annotated fig. 15 of Kim above); and
an upper post (113a) [0115] on the lower post and (electrically) connected to the redistribution layer (collective 112, 142 redistribution material) [0066, 0113], and wherein a (maximum) width of the lower post (113b) is greater than a (minimum) width of the upper post (113a) (slanted edges of 113 created different widths in and between individual 113s [0115]).
Regarding claim 10, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches, further comprising at least one third semiconductor chip (126) [0113] mounted on (supported by) the redistribution layer (collective 112, 142 redistribution material) [0066, 0113].
Regarding claim 11, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches, further comprising a second dummy chip (126) [0113] on (supported by) the redistribution layer (collective 112, 142 redistribution material) [0066, 0113].
Regarding claim 13, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches wherein, when viewed in a plan view (see also fig. 14) [0113-0115], the plurality of conductive posts include a first column of conductive posts (113) [0115] and a second column of conductive posts (160) [0115], and the chip stack (125s) [0115] and the second semiconductor chip (120) [0115] are disposed in a space (diagonally) between the first column of conductive posts (113s) and the second column of conductive posts (left 160s).
Regarding claim 14, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim wherein each of the plurality of conductive posts (113s, 160s) [0113-0115] has a pillar shape (portion) that extends in a (vertical) direction perpendicular to a top surface of the interposer substrate (comprising 150 with 160) [0066].
Regarding claim 15, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 1. Kim also teaches wherein the plurality of conductive posts (including middle 143) are disposed (partially) in a space between the chip stack (125) [0115] and the second semiconductor chip (120) [0115].
Regarding claim 30, Kim teaches a semiconductor package (100E) fig. 15 [0115], comprising (refer to annotated fig. 15 below):
a package substrate (184) [0066, 0097];
an interposer substrate (comprising 150 with 160) [0066] on (supported by) the package substrate (184);
a chip stack (stack of 125’s) [0115] on (supported by) the interposer substrate (comprising 150 with 160) and including a plurality of first semiconductor chips (memory chips 125s) [0115] that are vertically stacked;
a second semiconductor chip (120) [0115] (processor/logic chip 120) [0032, 0078, 0115] on (supported by) the interposer substrate (comprising 150 with 160) [0066] and horizontally spaced apart from the chip stack (125s);
a molding layer (130) [0113] disposed on (supported by) the interposer substrate (comprising 150 with 160) [0066] and surrounding a side surface of each of the chip stack (125s) and the second semiconductor chip (120);
a redistribution layer (141 hosting collective 112, 142 redistribution material) [0066, 0083, 0113] on the molding layer (130); and
a vertical connection terminal (comprising 113 a-b posts) [0087-0088] that vertically penetrates the molding layer (130) and connects the interposer substrate (comprising 160 in 150) [0066] to the redistribution layer (comprising 112s, 142s) (160, 142 with 112, and 113 are mutually-interconnected conductive layers [0091, 0075, 0085, 0115]).
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Annotated fig. 15 of Kim showing flipped perspective package considered from
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 19-21, 25-26, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2018/0076156A1) (of record) in view of Kim-II (U.S. PG Pub No US2021/0167054A1).
Regarding claim 19, Kim teaches a semiconductor package (100E) fig. 15 [0115], comprising (refer to annotated fig. 15 below):
a substrate (comprising 150 with 160) [0066];
a chip stack (stack of 125’s) [0115] on the substrate (comprising 150 with 160) [0066] and including a plurality of memory chips (125) [0115] that are vertically stacked;
a logic chip (120) [0115] (processor/logic chip 120) [0032, 0078, 0115] on (supported by) the substrate (comprising 150 with 160) [0066] and horizontally spaced apart from the chip stack (125’s);
a molding layer (130) [0113-0115] that surrounds a side surface off each of the chip stack (125s) and the logic chip (120);
a redistribution layer (collective 112, 142 redistribution material) [0066, 0113] on the molding layer (130) and having a through hole (110Ha) [0115] (partially) above the logic chip (120), the through hole (110Ha) (partially) penetrating the redistribution layer (comprising 142 material) (see annotated fig. 15 below) in a vertical direction perpendicular to a top surface of the substrate (comprising 150 with 160) [0066].
[AltContent: oval][AltContent: connector][AltContent: arrow][AltContent: textbox (Portion of 110Ha partially penetrating 142)]
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Annotated fig. 15 of Kim showing flipped perspective package considered from
However, Kim does not explicitly disclose wherein the through hole (110Ha) overlaps a top surface of the logic chip (120) in the vertical direction; and
a dummy chip in the through hole (110Ha) and contacting the top surface of the logic chip (120).
Kim-II teaches a semiconductor package (1000) fig. 2 [0022] wherein the through hole (gap through 240, 250 material hosting 300, 400) fig. 2 [0031-0032] overlaps a top surface of the logic chip (300) fig. 2 [0030] in the vertical direction; and
a dummy chip (400 with 500) fig. 2 [0032-0033] in the through hole (gap through 240, 250 material hosting 300, 400) fig. 2 [0031-0032] and (directly) contacting the top surface of the logic chip (300).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have expanded the through hole of Kim to overlap the logic chip and include the dummy chip of Kim-II [0031-0032] in order to compensate for a difference in height where the memory chips are stacked [0031-0033] so as to improve the integration density of vertically-stacked memory chips [0025, 0031-0032], as taught by Kim-II.
Regarding claim 20, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 19. Kim also teaches further comprising a vertical connection terminal (comprising 113 a-b posts) [0087-0088] that vertically penetrates the molding layer (130) [0113-0115] and (electrically) connects the substrate (comprising 150 with 160) [0066] to the redistribution layer (collective 112, 142 redistribution material) [0066, 0113].
Regarding claim 21, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 20. Kim also teaches wherein the vertical connection terminal (113) [0115] includes a conductive post (113b) extends in a vertical direction.
Regarding claim 25, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 19. Kim also teaches wherein:
the top surface of the logic chip (120) [0115] (processor/logic chip 120) [0032, 0078, 0115] is coplanar (in vertical plane) with a top surface of the molding layer (130), and the through hole (110Ha gap with attached 141 gaps) [0113-0115] exposes the top surface of the logic chip (120).
Regarding claim 26, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 19. Kim also teaches wherein:
the top surface of the logic chip (120) [0115] (processor/logic chip 120) [0032, 0078, 0115] is at a level lower than a level of a top surface of the molding layer (130), and the through hole (110Ha and 141 gaps) (partially) penetrates the redistribution layer (collective 112, 142 redistribution material) [0066, 0113] and an upper portion of the molding layer (130) and exposes the top surface of the logic chip (120) (see annotated fig. 15 above).
Regarding claim 28, Kim teaches the semiconductor package (100E) fig. 15 [0115] of claim 19. Kim also teaches further comprising at least one additional semiconductor chip (126, 127) fig. 15 [0113-0115] mounted on (supported by) the redistribution layer (collective 112, 142 redistribution material) [0066, 0113].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 30 have been considered but are moot because the new ground of rejection relies upon a reinterpretation of the interposer substrate to be elements 150 with 160 [see fig. 15, 0066 Kim] such that the interposer substrate comprising 160 and the redistribution material comprising 142 are mutually-electrically-interconnected conductive layers [0091, 0075, 0085, 0115].
Applicant’s arguments, see pages 5-7, filed 02/02/2026, with respect to the rejection(s) of claim(s) 19 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim-II (U.S. PG Pub No US2021/0167054A1) under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they all feature package structures with a variety of chips.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/11/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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