Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-21 are pending and examined below.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ELECTRONIC DEVICES HAVING EMBEDDED MODULE AND METHODS OF MANUFACTURING ELECTRONIC DEVICES HAVING THE SAME
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11, 15, 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2022/0028774 A1 to Murayama et al. ("Murayama").
Fig. 2 and Fig. 1A of Murayama have been annotated to support the rejection below:
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Regarding independent claim 1, Murayama teaches an electronic device (see Fig. 2 and Fig. 1A), comprising:
a first embedded module 30, 31, 71 (para [0044] - “Each semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a bonding portion 71 having an electrical conductivity…electrode pad 31…”) comprising:
a first module substrate 71; and
a first module component 30 (para [0027] - “one or more semiconductor elements 30 (for example, two, refer to FIGS. 2 and 3) mounted on the upper surface of the lower substrate 20…”) coupled to the first module substrate 71;
a first device substrate 20, 21, 22 and/or 26 (para [0035] - “As illustrated in FIGS. 2 and 3, for example, a wiring layer 21 is formed on the upper surface of the lower substrate 20. The wiring layer 21 includes, for example, one or more (for example, one) wiring pattern 22, one or more (for example, two) wiring patterns 23, and one or more (for example, two) wiring patterns 24.”; para [0042] - “As illustrated in FIG. 1A, for example, a metal layer 26 is formed on the lower surface of the lower substrate 20.”) coupled to the first module substrate 71;
device terminals 24 (para [0047] - “wiring patterns 24”) coupled to the first module substrate 71 (via lower substrate 20 and wiring patter 22); and
a device encapsulant structure 50 (para [0066] -“encapsulation resin 50”) encapsulating the first embedded module 30, 31, 71, the device terminals 24; and the first device substrate 20, 21, 22 and/or 26;
wherein:
a portion P1 of the first device substrate 20, 21, 22 and/or 26 is exposed from the device encapsulant structure 50; and
portions P2 of the device terminals 24 are exposed from the device encapsulant structure 50.
Regarding claim 11, Murayama teaches a second device substrate 40, 60 coupled to the first module component 30;
wherein:
the second device substrate 40, 60 is exposed from the device encapsulant structure 50 (see Fig. 2; see also Fig. 1A).
Regarding claim 15, Murayama teaches an electronic device (see Fig. 2 of Fig. 1A), comprising:
a first embedded module 30, 31, 71, 22 comprising:
a first module substrate 22 or 22, 71 (para [0044] - “Each semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a bonding portion 71 having an electrical conductivity.”); and
a first module component 30 (para [0027] - “one or more semiconductor elements 30 (for example, two, refer to FIGS. 2 and 3) mounted on the upper surface of the lower substrate 20…”) coupled to the first module substrate 22 or 22, 71;
a first device substrate 20, 21 and/or 26 (para [0035] - “As illustrated in FIGS. 2 and 3, for example, a wiring layer 21 is formed on the upper surface of the lower substrate 20. The wiring layer 21 includes, for example, one or more (for example, one) wiring pattern 22, one or more (for example, two) wiring patterns 23, and one or more (for example, two) wiring patterns 24.”; para [0042] - “As illustrated in FIG. 1A, for example, a metal layer 26 is formed on the lower surface of the lower substrate 20.”) coupled to the first module substrate 22 or 22, 71;
device terminals 24 (para [0047] - “wiring patterns 24”) coupled to the first module substrate 22 or 22, 71 (via lower substrate 20); and
a device encapsulant structure 50 (para [0066] -“encapsulation resin 50”) encapsulating the first embedded module 30, 31, 71, 22, the device terminals 24; and the first device substrate 20, 21 and/or 26;
wherein:
a portion P1 of the first device substrate 20, 21 and/or 26is exposed from the device encapsulant structure 50; and
portions P2 of the device terminals 24 are exposed from the device encapsulant structure 50,
a second module component 30 (see Fig. 2) coupled to the first module substrate 22 or 22, 71; wherein:
the first module substrate 22 or 22, 71 comprises a routable molded lead frame 22; and
the first module component 30 and the second module component 30 reside on a same plane (see Fig. 2; see also Fig. 1A).
Regarding independent claim 16, Murayama teaches an electronic device (see Fig. 2 and Fig. 1A), comprising:
a first embedded module 30, 31, 71, 40, 60, 61, 32 (para [0044] - “Each semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a bonding portion 71 having an electrical conductivity…electrode pad 31…”; para [0049] - “…upper substrate 40…the wiring layer 60…”; para [0052] - “electrode pads 32 and 33”) comprising:
a first module substrate 71 comprising a first conductive structure 71;
a second module substrate 60 comprising a second conductive structure 61; and
a first module component 30, 31 interposed between the first module substrate 71 and the second module substrate 40, 60, the first module component 30, 31 comprising:
a first component terminal 31 coupled to the first conductive structure 71; and
a second component terminal 32 coupled to the second conductive structure 61;
a first device substrate 22, 21, 20, 26 coupled to the first module substrate 71 and comprising a first outward conductive layer 22 (see Fig. 2);
a second device substrate 40, 62 coupled to the first module component 30, 31 and comprising a second outward conductive layer 62;
device terminals 24 coupled to the first module component 30, 31; and
a device encapsulant structure 50 encapsulating the first embedded module 30, 31, 71, 40, 60, 32, the first device substrate 22, 21, 20, 26, the second device substrate 40, and the device terminal 24;
wherein:
the device terminals 24, the first outward conductive layer 22 (see Fig. 2), and the second outward conductive layer 62 (see Fig. 1A) are exposed from the device encapsulant structure 50.
Regarding independent claim 19, Murayama teaches an electronic device (see Fig. 2 and Fig. 1A) teaches a method of manufacturing an electronic device, comprising:
providing a first embedded module 71, 22, 60, 40, 30, 31, 32, 33 comprising:
a first module substrate 71, 22 comprising a first conductive structure 71;
a second module substrate 60, 40 comprising a second conductive structure 60; and
a first module component 30, 31, 32, 33 interposed between the first module substrate 71, 22 and the second module substrate 60, 40, the first module component 30, 31, 32, 33 comprising:
a first component terminal 31 coupled to the first conductive structure 71; and
a second component terminal 33 coupled to the second conductive structure 60; and
providing a first device substrate 20, 26 coupled to the first module substrate 71, 22 and comprising a first outward conductive layer 22;
providing a second device substrate 21 coupled to the first module component 30, 31, 32, 33 and comprising a second outward conductive layer 21;
providing device terminals 61, 62 coupled to the first module component 30, 31, 32, 33; and
providing a device encapsulant structure 50 encapsulating the first embedded module 71, 22, 60, 40, 30, 31, 32, 33, the first device substrate 20, 26, the second device substrate 21, and the device terminals 61, 62;
wherein:
the device terminals 61, 62, the first outward conductive layer 22, and the second outward conductive layer 21 are exposed from the device encapsulant structure 50.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2.
Claims 3-10 are allowable for depending on the allowable claim 2.
Claim 12 is objected to for depending on a rejected base claim 1 and the intervening claim 11, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 11 or the base claim 1 is amended to include all of the limitations of claim 12 and the intervening
claim 11.
Claim 13 is allowable for depending on the allowable claim 12.
Claim 14 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 14.
Claim 17 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 17.
Claim 18 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 18.
Claim 20 is objected to for depending on a rejected base claim 19, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 19 or the base claim 19 is amended to include all of the limitations of claim 20.
Claim 21 is objected to for depending on a rejected base claim 19, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 19 or the base claim 19 is amended to include all of the limitations of claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Patent No. US 9,953,913 B1 to Gowda et al.
Pub. No. US 2023/0231487 A1 to Kusukawa et al.
Pub. No. US 2022/0392828 A1 to Kato et al.
Pub. No. US 2013/0241040 A1 to Tojo et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 06 November 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status