DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2020/0091036 A1 hereinafter referred to as “Chen”).
With respect to claim 1, Chen discloses, in Figs.1-18, an electronic device, comprising: a heat generating element (12) and a direct vapor chamber (16) including an upper part (163), a lower part (164), a two-phase heat dissipating structure (163-164), and a working liquid (166); wherein the lower part (164) includes the heat generating element (12) as a portion of it; and the upper part (163) and the lower part (164) form a closed chamber (16); and wherein the two phase heat dissipating structure (163-164) is formed inside the closed chamber (16); and the working liquid (166) works in the two phase heat dissipating structure (163-164) to directly dissipate a heat from the heat generating element (12) to the upper part through a phase change/(liquid-gas phase) manner (31) (see Par.[0031]-[0032] wherein the package substrate 10 may further include a die mounting portion 103 for receiving the semiconductor die 12; see Par.[0033]-[0035] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; see Par.[0039] wherein as shown in FIG. 3, during the operation of the semiconductor die 12, the heat generated by the semiconductor die 12 will be absorbed by the first working liquid 166 on the first portion 1621 of the bottom wall 162 of the vapor chamber 16 (e.g., the central portion of the vapor chamber 16) to heat the first working liquid 166 become high-temperature fluid or high-temperature vapor; the heated first working liquid 166 (e.g., high-temperature fluid or high-temperature vapor) will move upwardly to the top wick structure 163, as shown in the first path 31).
With respect to claim 2, Chen discloses, in Figs.1-18, the electronic device, further comprising: a substrate (10), a lid (1622) with a window (149) and a sealing ring (141); wherein the heat generating element (12) is a flip chip mounted on the substrate (24) and exposed from the window (149), the sealing ring (141) is positioned at a peripheral edge region of the flip chip (12) so as to seal a gap between the lid (1622) and the flip chip (12), and the lower part includes the lid (1622), the flip chip (12) and the sealing ring (141) (see Par.[0036] wherein the bottom wall 162 includes a first portion 1621 and a second portion 1622 surrounding the first portion 1621; the first portion 1621 corresponds to a central portion of the vapor chamber 16, and the second portion 1622 corresponds to a periphery portion of the vapor chamber 16; see Par.[0033] wherein the inner lateral wall 141 is a ring shape and defines a through hole 149; see Par.[0031]-[0032] wherein the package substrate 10 has a first surface 101 (e.g., a top surface) and a second surface 102 (e.g., a bottom surface) opposite to the first surface 101, and may include a plurality of passivation layers (i.e.; passivation layers are of non-circuit layer such as dielectric or insulating material which are moldable) and at least one circuit layer (e.g., redistribution layer, RDL) interposed between the passivation layers; the semiconductor die 12 is attached to the die mounting portion 103 of the package substrate 10, and is electrically connected to the first surface 101 of the package substrate 10 through the inner connecting elements 17 (e.g., solder bumps) by flip-chip bonding).
With respect to claim 3, Chen discloses, in Figs.1-18, the electronic device, further comprising: a substrate (10) and a molding material (13) (see Par.[0037] wherein the thermal paste 13 may be a thermal interface material (TIM) with a thermal conductivity of about 30 W/mK to about 40 W/mK. A thickness of the thermal paste 13 may be about 0.1 mm; the thermal paste 13 (e.g., a thermal interface material (TIM)) is used to adhere the first surface 121 of the semiconductor die 12 to the bottom surface of the first portion 1621 of the bottom wall 162 of the vapor chamber 16); wherein the heat generating element is a flip chip (12) mounted on the substrate (10), the molding material (13) covers a top surface of the substrate (10) around the flip chip (12), and the lower part includes the flip chip (12) and the molding material (13).
With respect to claim 4, Chen discloses, in Figs.1-18, the electronic device, further comprising: a substrate (10), a stiffener (143-144), and a molding material (13, 15); wherein the heat generating element is a flip chip (12) mounted on the substrate (10), the stiffener (143-144) is mounted on a peripheral region of the substrate (10), the molding material (13, 15) covers a top surface of the substrate between the flip chip (12) and the stiffener (143-144), and the lower part includes the flip chip (12), the stiffener (143-144), and the molding material (13, 15) (see Par.[0031], [0038] wherein he semiconductor package structure 1 includes a package substrate 10, at least one semiconductor die 12, a thermal paste 13, a heat dissipating device 14, a thermal adhesive tape 15, a vapor chamber 16, a plurality of inner connecting elements 17 (e.g., solder bumps) and a plurality of external connecting elements 18 (e.g., solder bumps); the second portion 1622 of the bottom wall 162 of the vapor chamber 16 is thermally connected and physically connected to the top surface of the heat dissipating device 14 through the thermal adhesive tape 15; see Par.[0034] wherein the inner lateral wall 141, the outer lateral wall 142 and the lower wall 144 may be formed integrally, and then the upper wall 143 covers the inner lateral wall 141 and the outer lateral wall 142).
With respect to claim 5, Chen discloses, in Figs.1-18, the electronic device, wherein the two-phase heat dissipating structure (162, 161) includes a plurality of channels/(channels between wicks bars 165) formed at a bottom surface of the upper part and a layer of wick clamped between the upper part and the lower part (see Par.[0035] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166).
With respect to claim 6, Chen discloses, in Figs.1-18, the electronic device, wherein the two-phase heat dissipating structure includes a layer of wick at a bottom surface of the upper part, another layer of wick at a top surface of the lower part, and a space between the two layers of wicks (see Par.[0035]-[0036] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; the vapor chamber 16 may not have a consistent thickness, and the wick bars 165 may not have a consistent length. The length of the wick bar 165 corresponding to the first portion 1621 (e.g., the central portion) is greater than the length of the wick bar 165 corresponding to the second portion 1622 (e.g., the periphery portion)).
With respect to claim 7, Chen discloses, in Figs.1-18, the electronic device, wherein the heat generating element comprises a chip module or a plurality of chips or chiplets (see Par.[0031] wherein the semiconductor package structure 1 includes a package substrate 10, at least one semiconductor die 12 (i.e.; at lost pluralities of chips), a thermal paste 13, a heat dissipating device 14, a thermal adhesive tape 15, a vapor chamber 16, a plurality of inner connecting elements 17 (e.g., solder bumps) and a plurality of external connecting elements 18 (e.g., solder bumps)).
With respect to claim 8, Chen discloses, in Figs.1-18, the electronic device, wherein the upper part and the lower part are assembled together through an adhesive or a direct welding at their peripheral regions to form the closed chamber (see Par.[0047] wherein the second portion 1622b of the bottom wall 162b of the vapor chamber 16b may be physically connected to the first surface 101 of the package substrate 10 through an adhesive tape 15b. The adhesive tape 15b may be or may not be a thermal adhesive tape).
With respect to claim 9, Chen discloses, in Figs.1-18, the electronic device, wherein the upper part and the lower part are assembled together through another sealing ring (144/51a) at their peripheral regions to form the closed chamber (see Par.[0033] wherein the inner lateral wall 141 is a ring shape and defines a through hole 149. The outer lateral wall 142 surrounds the inner lateral wall 141).
With respect to claim 10, Chen discloses, in Figs.1-18, the electronic device, wherein the upper part includes a base plate and a cooler on a top surface of the base plate (see Par.[0039]-[0040] wherein the high-temperature fluid or high-temperature vapor in or near the top wick structure 163 will be cooled by the second working liquid 30 of the heat dissipating device 14 to become low-temperature liquid or low-temperature vapor, and then will move downwardly along the wick bars 165, as shown in the third path 33).
With respect to claim 11, Chen discloses, in Figs.1-18, the electronic device, wherein the working liquid is water (see Par.[0045] wherein the second working liquid 30 may be water. As shown in FIG. 8, the covering wall 44 of the heat dissipating device 14a is a hat type).
With respect to claim 12, Chen discloses, in Figs.1-18, the electronic device, wherein the upper part includes a base plate with a pedestal extending into the window.
With respect to claim 13, Chen discloses, in Figs.1-18, the electronic device, wherein the lower part further includes a metal layer plated on a top surface of the flip chip and the molding material.
With respect to claim 14, Chen discloses, in Figs.1-18, the electronic device, wherein the lower part further includes a metal layer plated on a top surface of the flip chip, the stiffener, and the molding material.
With respect to claim 15, Chen discloses, in Figs.1-18, the electronic device, wherein the layer of wick is formed through one or more layers of copper meshes (see Par.[0035] wherein the material of the top wall 161 and the bottom wall 162 may be copper, copper alloy, aluminum alloy, stainless steel or other suitable metal).
With respect to claim 16, Chen discloses, in Figs.1-18, the electronic device of claim 6, wherein the upper part includes a base plate with a plurality of posts/(central portion longer vertical wicks) extending into the space between the two layers of wicks (see Par.[0035]-[0036] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; the vapor chamber 16 may not have a consistent thickness, and the wick bars 165 may not have a consistent length. The length of the wick bar 165 corresponding to the first portion 1621 (e.g., the central portion) is greater than the length of the wick bar 165 corresponding to the second portion 1622 (e.g., the periphery portion)).
With respect to claim 17, Chen discloses, in Figs.1-18, the electronic device, wherein one or more spacers/(central portion longer vertical wicks) are positioned in the space between the two layers of wicks (see Par.[0035]-[0036] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; the vapor chamber 16 may not have a consistent thickness, and the wick bars 165 may not have a consistent length. The length of the wick bar 165 corresponding to the first portion 1621 (e.g., the central portion) is greater than the length of the wick bar 165 corresponding to the second portion 1622 (e.g., the periphery portion)).
With respect to claim 18, Chen discloses, in Figs.1-18, a lidded flip chip package, comprising: a substrate (10), a lid (1621-1622) mounted on the substrate (10), a flip chip (12) mounted on the substrate (10), a sealing ring (141), and a direct vapor chamber (16) including a lower part (162), an upper part (161), a two-phase heat dissipating structure (163-164), and a working liquid (166); wherein the lid has a window (149), the flip chip (12) is exposed from the window (149), and the sealing ring (141) is positioned at a peripheral edge region of the flip chip (12) to seal a gap between the lid (1622) and the flip chip (12); wherein the lower part (162) comprises of the lid (1621-1622), the sealing ring (141), and the flip chip (12), the upper part (163-164) includes a base plate with a pedestal/(central portion longer vertical wicks) extending into the window (149), the upper part and the lower part are assembled together at their peripheral regions so as to form a closed chamber (16); and wherein the two-phase heat dissipating structure (162, 161) is formed inside the closed chamber, which includes a layer of wick (165) at a top surface of the low part, and the working liquid (166) works in the two phase heat dissipating structure to directly dissipate a heat from the flip chip (12) to the upper part through a phase change/(liquid-gas phase) manner (see Par.[0031]-[0032] wherein the package substrate 10 may further include a die mounting portion 103 for receiving the semiconductor die 12; see Par.[0033]-[0035] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; see Par.[0039] wherein as shown in FIG. 3, during the operation of the semiconductor die 12, the heat generated by the semiconductor die 12 will be absorbed by the first working liquid 166 on the first portion 1621 of the bottom wall 162 of the vapor chamber 16 (e.g., the central portion of the vapor chamber 16) to heat the first working liquid 166 become high-temperature fluid or high-temperature vapor; the heated first working liquid 166 (e.g., high-temperature fluid or high-temperature vapor) will move upwardly to the top wick structure 163, as shown in the first path 31; see Par.[0036] wherein the bottom wall 162 includes a first portion 1621 and a second portion 1622 surrounding the first portion 1621; the first portion 1621 corresponds to a central portion of the vapor chamber 16, and the second portion 1622 corresponds to a periphery portion of the vapor chamber 16; see Par.[0033] wherein the inner lateral wall 141 is a ring shape and defines a through hole 149; see Par.[0031]-[0032] wherein the package substrate 10 has a first surface 101 (e.g., a top surface) and a second surface 102 (e.g., a bottom surface) opposite to the first surface 101, and may include a plurality of passivation layers (i.e.; passivation layers are of non-circuit layer such as dielectric or insulating material which are moldable) and at least one circuit layer (e.g., redistribution layer, RDL) interposed between the passivation layers; the semiconductor die 12 is attached to the die mounting portion 103 of the package substrate 10, and is electrically connected to the first surface 101 of the package substrate 10 through the inner connecting elements 17 (e.g., solder bumps) by flip-chip bonding; see Par.[0035]-[0036] wherein the vapor chamber 16 includes a top wall 161, a bottom wall 162, a top wick structure 163, a bottom wick structure 164, a plurality of wick bars 165 and a first working liquid 166; the vapor chamber 16 may not have a consistent thickness, and the wick bars 165 may not have a consistent length. The length of the wick bar 165 corresponding to the first portion 1621 (e.g., the central portion) is greater than the length of the wick bar 165 corresponding to the second portion 1622 (e.g., the periphery portion)).
With respect to claim 19, Chen discloses, in Figs.1-18, the lidded flip chip package, wherein the flip chip comprises a chip module or a plurality of chip lets (see Par.[0031] wherein the semiconductor package structure 1 includes a package substrate 10, at least one semiconductor die 12 (i.e.; at lost pluralities of chips), a thermal paste 13, a heat dissipating device 14, a thermal adhesive tape 15, a vapor chamber 16, a plurality of inner connecting elements 17 (e.g., solder bumps) and a plurality of external connecting elements 18 (e.g., solder bumps)).
With respect to claim 20, Chen discloses, in Figs.1-18, the lidded flip chip package, wherein the upper part further includes a cooler on a top surface of the base plate (see Par.[0039]-[0040] wherein the high-temperature fluid or high-temperature vapor in or near the top wick structure 163 will be cooled by the second working liquid 30 of the heat dissipating device 14 to become low-temperature liquid or low-temperature vapor, and then will move downwardly along the wick bars 165, as shown in the third path 33).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818