Prosecution Insights
Last updated: April 18, 2026
Application No. 18/235,955

Field Effect Transistor Constructions and Methods of Programming Field Effect Transistors to One Of At Least Three Different Programmed States

Non-Final OA §112
Filed
Aug 21, 2023
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
80%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
358 granted / 546 resolved
-2.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
40 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§112
Attorney’s Docket Number: MI22- 8 553 Filing Date: 8/21/2023 Claimed Priority Date s : 10/14/2021 (US 17/501,464) 6/19/2018 (US 16/011,771) 4/24/2014 (US 14/260,940) Inventor s: Karda et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the election and amendment filed on 3/2/2026 . Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA (or as subject to pre-AIA) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The amendment filed on 3/2/2026 in reply to the Office action in paper no. 4, mailed on 2/26/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 29-55. Election Applicant’s election of invention II, reading on a semiconductor device, and species 7, reading on figure 5 in view of figure 7, in the reply filed on 3/2/2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). The applicant indicates that claims 36-55 read on the elected invention and species. Claims 36-42, however, read on a non-elected species of the claimed invention. Accordingly, claims 29-42 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 43-55 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claims contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. C laim 43 recites a gate insulator having at least three sides with three different thicknesses, and claim 49 recites a gate insulator comprising at least three pairs of opposite sides. The specification does not enable the full scope of these claims. The only specific manufacturing process disclosed in the application is described in ¶0037, which teaches forming four-sided channel cores using orthogonally oriented trenches, followed by deposition of gate insulator material to achieve differ ent thicknesses on opposing sides. However, this process is limited to rectangular (four-sided) channel structures and does not provide sufficient guidance for forming non-rectangular geometries, including the elected embodiment of FIG. 7, which comprises a hexagonal channel core with three pairs of opposing regions having different thicknesses. Although ¶0037 states that “additional or alternate processing may occur” by masking or exposing different circumferential locations, the specification does not describe any specific process steps, patterning techniques, or deposition schemes that would enable a person of ordinary skill in the art to fabricate the claimed structures across the full scope of the claims without undue experimentation. In particular, the specification fails to teach how to achieve controlled, circumferentially varying thickness profiles across more complex geometries such as hexagonal channel cores having multiple pairs of regions with differing thicknesses. Considering the factors set forth in In re Wands , undue experimentation would be required. Specifically, (1) the breadth of the claims encompasses multiple geometries and configurations beyond the disclosed rectangular embodiment, (2) the specification provides only limited guidance directed to a single fabrication approach, (3) there is an absence of working examples or detailed teachings for non-rectangular embodiments, and (4) the required experimentation would involve developing non-trivial fabrication processes to achieve the claimed circumferential thickness variations in more complex geometries. Accordingly, the specification does not enable the full scope of claims 43 and 49 without undue experimentation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9 :00 AM to 7:0 0 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov . If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 ( in USA or Canada ) or 571-272-1000. /Marcos D. Pizarro/ Primary Examiner, Art Unit 2814 MDP/mdp DATE \@ "MMMM d, yyyy" April 1, 2026
Read full office action

Prosecution Timeline

Aug 21, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12568612
Arrays Of Capacitors, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming An Array Of Capacitors
2y 5m to grant Granted Mar 03, 2026
Patent 12557215
SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGY
2y 5m to grant Granted Feb 17, 2026
Patent 12557710
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Feb 17, 2026
Patent 12541113
IMAGE SENSOR INCLUDING COLOR SEPARATING LENS ARRAY AND ELECTRONIC DEVICE INCLUDING THE IMAGE SENSOR
2y 5m to grant Granted Feb 03, 2026
Patent 12543370
THIN-FILM TRANSISTOR ARRAY SUBSTRATE WITH CONNECTION NODE AND DISPLAY DEVICE INCLUDING THE SAME
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
80%
With Interview (+14.8%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month