Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/21/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-13, and 16-20 without traverse in the reply filed on 02/09/2026 is acknowledged.
Claim Objections
Claims 1 and 16 are objected to because of the following informalities:
Claim 1 recites the limitation, “a plurality of through-electrodes electrically respectively connecting the plurality of upper pads and the plurality of lower pads”. The Examiner believes the Applicant intended to recite, “a plurality of through-electrodes respectively electrically connecting the plurality of upper pads and the plurality of lower pads”.
Claim 16 recites the limitation, “a second group of through-electrode around the first group of through-electrodes”. The Examiner believes the Applicant intended to recite, “a second group of through-electrodes around the first group of through-electrodes”.
Claim 16 recites the limitation, “and a second group of lower pads electrically connected to the second group of lower pads ” The Examiner believes the Applicant intended to recite, “and a second group of lower pads electrically connected to the second group of upper pads”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Claim 1 recites the limitation, “a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads ”. The Examiner finds this limitation to be indefinite because it is not clear what is meant by, “each other of the second group of upper pads”. The Applicant could mean that there are several second groups of upper pads which are each connected to upper pads. The Applicant could also mean that there are alternating second groups of upper pads which are connected to upper pads. From the Applicant’s FIG. 1, the Examiner believes the Applicant means that there are upper pads within the second group of upper pads which are electrically connected to each other.
Regarding Claims 2-13, these claims depend upon claim 1 and are rejected for the same reasons.
Regarding Claim 8,
Claim 8 recites, “wherein the second group of lower pads includes a via portion extending into the lower insulating layer and electrically insulated from the lower interconnection layer.” The Examiner finds this recitation to be indefinite because it is not clear what is electrically insulated from the lower interconnection layer. From Applicant’s FIG. 2B, it appears that the second group of lower pads is insulated from the lower interconnection layer. The Examiner therefore interprets the recitation to mean, “wherein the second group of lower pads includes a via portion extending into the lower insulating layer; wherein the lower pads are electrically insulated from the lower interconnection layer”.
Regarding Claim 10,
Claim 10 recites the limitation, “and a pattern portion on the upper insulating layer and extending between upper pads of the plurality of upper pads that are electrically connected to each other”. The Examiner finds the limitation to be indefinite because it is not stated what is extending between upper pads of the plurality of upper pads that are electrically connected to each other. From the Applicant’s figures and specification, the Examiner believes the Applicant intended for the pattern portion to extend between upper pads of the plurality of upper pads that are electrically connected to each other. Therefore, the Examiner interprets the recitation to mean, “and a pattern portion on the upper insulating layer, wherein the pattern portion extends between upper pads of the plurality of upper pads that are electrically connected to each other”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 9, and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al US 20200161242 A1. Lin et al will be referenced to as Lin henceforth.
Regarding Claim 1,
Lin teaches:
“A semiconductor package (FIG. 15A), comprising:
a first semiconductor chip ([0387], annotated FIG. 15A #1), at least one second semiconductor chip (annotated FIG. 15A #1), and a third semiconductor chip (annotated FIG. 15A #1), sequentially stacked in a vertical direction and electrically connected to each other (annotated FIG. 15A #1: The chips are electrically connected by the interconnects 696.);
an encapsulant on the first semiconductor chip (molding compound 695, [0396]), the encapsulant encapsulating at least a portion of each of the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip (FIG. 15A: 695 encapsulates a top portion of the first semiconductor chip and a side portion of both the at least one second semiconductor chip and the third semiconductor chip.);
and a plurality of external connection bumps below the first semiconductor chip (micro-bumps 34, [0397]), the plurality of external connection bumps being electrically connected to the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip (annotated FIG. 15A #1: The chips are electrically connected to the micro-bumps by the interconnects 696 and TSVs 157.), wherein:
the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip each include a plurality of lower pads (copper layer 48, [0414], annotated FIG. 15A #2, FIG. 16B: 48 pads a lower side of bonded contact 158), the first semiconductor chip and the at least one second semiconductor chip each include:
a plurality of upper pads (copper layer 37, [0414], annotated FIG. 15A #2, FIG. 16B) including a first group of upper pads (annotated FIG. 15A #2) and a second group of upper pads (annotated FIG. 15A #2), and a plurality of through-electrodes electrically respectively connecting the plurality of upper pads and the plurality of lower pads (Through silicon vias (TSV) 157, [0395]: The TSVs connect the upper pads of a lower set of pads to the lower pads of an upper set of pads.), and the plurality of through-electrodes includes:
a first group of through-electrodes respectively connected to the first group of upper pads (annotated FIG. 15A #2), and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads (annotated FIG. 15A #2: The multiple interconnect 696 electrically connects each other of the second group of upper pads.).”
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Annotated FIG. 15A #1
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Annotated FIG. 15A #2
Regarding Claim 2,
Lin teaches:
“The semiconductor package as claimed in claim 1, wherein a separation distance between through-electrodes of the second group of through-electrodes is equal to or greater than a separation distance between through-electrodes of the first group of through-electrodes (annotated FIG. 15A #3: The separation distance is the same.).”
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Annotated FIG. 15A #3
Regarding Claim 3,
Lin teaches:
“The semiconductor package as claimed in claim 1, wherein the first group of through-electrodes are electrically insulated from the second group of through-electrodes ([0388], annotated FIG. 15A #2: TSVs 157 are insulated by semiconductor substrate 2.). ”
Regarding Claim 5,
Lin teaches:
“The semiconductor package as claimed in claim 1, wherein:
the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip each further include a lower interconnection layer between the plurality of lower pads and the plurality of through-electrodes (interconnection metal layers 6, [0388], [0396], FIG. 14C: Notice FIG. 15A uses the HBM IC chips as shown in FIG. 14C.), and a lower insulating layer in which the lower interconnection layer is buried (insulating dielectric layers 12, [0364], FIG. 14C), and the plurality of lower pads includes:
a first group of lower pads connected to the first group of through- electrodes by the lower interconnection layer (annotated FIG. 14C #1: the lower interconnection layer is electrically connected to both the lower pads and the first group of through-electrodes.), and a second group of lower pads electrically insulated from the first group of lower pads (annotated FIG. 14C #1: Layers 12 and 42 isolate the metal connections between the first lower pads and first through electrodes and the metal connections between the second lower pads and second through electrodes from each other. Note: the lower pads are not shown and are above 34. See FIG. 15A).”
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Annotated FIG. 15C #1
Regarding Claim 6,
Lin teaches:
“The semiconductor package as claimed in claim 5, wherein the second group of through-electrodes are connected to at least one lower pad of the second group of lower pads by the lower interconnection layer (annotated FIG. 14C #1). ”
Regarding Claim 9,
Lin teaches:
“The semiconductor package as claimed in claim 1, wherein:
the first semiconductor chip and the at least one second semiconductor chip each further include an upper interconnection layer between the plurality of upper pads and the plurality of through-electrodes (interconnection metal layer 27, [0426], annotated FIG. 14C #1), and an upper insulating layer in which the upper interconnection layer is buried (one or more polymer layers 42, [0426], annotated FIG. 14C #1), and the second group of through-electrodes is connected to upper pads of the plurality of upper pads that are electrically connected to each other by the upper interconnection layer (annotated FIG. 14C #1).”
Regarding Claim 11,
Lin teaches:
“The semiconductor package as claimed in claim 1, wherein the first semiconductor chip has a width that is greater than a width of the at least one second semiconductor chip and greater than a width of the third semiconductor chip (annotated FIG. 15A #1). ”
Regarding Claim 12,
Lin teaches:
“The semiconductor package as claimed in claim 11, wherein the width of the at least one second semiconductor chip and the width of the third semiconductor chip are substantially the same (annotated FIG. 15A #1).”
Regarding Claim 13,
Lin teaches:
“The semiconductor package as claimed in claim 1, further comprising:
a plurality of interconnection bumps between the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip (multiple bonded contacts 158, [0387], FIG. 15A), the plurality of interconnection bumps being electrically connected to the plurality of through- electrodes ([0388], [0391]: 158 is connected to 157 and both are electrically conductive.);
and a plurality of adhesive films surrounding the plurality of interconnection bumps between the first semiconductor chip, the at least one second semiconductor chip, and the third semiconductor chip (Underfill 694, [0394]: the underfill is made of a polymer. Applicant’s adhesive film is also made of a polymer.).”
Regarding Claim 20,
Lin teaches:
“A semiconductor package, comprising a plurality of semiconductor chips stacked in a vertical direction (annotated FIG. 15A #1), wherein:
at least one semiconductor chip among the plurality of semiconductor chips includes a substrate (substrate 2, [0395], FIG. 15A: The substrate is part of the first semiconductor chip.), a plurality of lower pads below the substrate (electroplated copper 32, [0388], [0394], FIG. 14C, FIG. 15A: the top part of 34 in FIG. 15A is 32.), a plurality of upper pads on the substrate (annotated FIG. 15A #5), and a plurality of through-electrodes penetrating through the substrate and electrically connected to at least one of the plurality of lower pads and the plurality of upper pads (annotated FIG. 15A #4, annotated FIG. 15A #5), and the plurality of through-electrodes includes:
a first group of through-electrodes connected to one upper pad among the plurality of upper pads (annotated FIG. 15A #4, annotated FIG. 15A #5: The lower through electrodes of the first group of through electrodes are electrically connected to both of the top through electrodes of the first group of through electrodes. Therefore, the lower through electrodes are electrically connected to both of the top upper pads. Therefore, the lower through electrodes of the first group of through-electrodes are connected to one upper pad among the plurality of upper pads.), and a second group of through-electrodes connected to two or more upper pads among the plurality of upper pads (annotated FIG. 15A #4, annotated FIG. 15A #5: the second group of through electrodes are electrically connected to two or more upper pads.).”
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Allowable Subject Matter
Claims 4, 7-8, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4,
Lin fails to explicitly teach :
“and the second group of through-electrodes includes dummy electrodes” In view of the rest of the limitations of claim 4.
Lin fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because Lin teaches that signal, power or ground delivery electrical signals may pass through interconnection metal layers 6, and therefore through the electrically connected through-electrodes. These electric signals are not used in dummy electrodes. Therefore none of the through electrodes are dummy electrodes.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin to reach all of the limitations of the claim.
Regarding Claim 7, this claim has a similar limitation to claim 4 and is objectionable for the same reasons.
Regarding Claim 8,
Lin fails to explicitly teach :
“wherein the second group of lower pads includes a via portion extending into the lower insulating layer and electrically insulated from the lower interconnection layer” In view of the rest of the limitations of claim 8.
Lin fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because the lower pads do not include a via portion extending into the lower insulating layer which are electrically insulated from the lower interconnection layer. Namely, in FIG. 14C, the via portions of the lower pads are all electrically connected to the lower interconnection layer.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin to reach all of the limitations of the claim.
Regarding Claim 10,
Lin fails to explicitly teach :
“a pattern portion on the upper insulating layer and extending between upper pads of the plurality of upper pads that are electrically connected to each other , and the second group of through-electrodes are connected to upper pads of the plurality of upper pads that are electrically connected to each other by the pattern portion” In view of the rest of the limitations of claim 10.
Lin fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because Lin does not have an upper insulating layer surrounding the plurality of through electrodes. Further there is no pattern portion on the upper insulating layer extending between electrically connected upper pads. The Examiner did find, US 20210407949 A1, which meets the limitations of the claim. However, this art is filed by the same Applicant within less than a year of the Applicant’s filing date and is therefore not prior art.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin to reach all of the limitations of the claim.
Claims 16-19 are allowable, the Examiner’s reasons for allowance are as follows:
Regarding Claim 16,
Lin fails to explicitly teach :
“wherein upper pads of the second group of upper pads, that are connected to each other, are connected to one through-electrode of the second group of through- electrodes” In view of the rest of the limitations of claim 16.
Lin fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because the second group of upper pads must be around the first group of upper pads. Because of the geometry of the invention of Lin in FIG. 15A, this means that the upper pads in the second group of upper pads cannot be electrically connected to one another. Therefore Lin cannot meet the above limitation.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lin to reach all of the limitations of the claim.
Regarding Claims 17-19, these claims depend on claim 16 and are allowable for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights