Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 1/30/2026. Applicant has elected Group II, corresponding to claims 1-7 and 12-15. Invention Group I, corresponding to claims 8-11, is withdrawn from further consideration.
Drawings
The drawings are objected to because Fig. 13 has an X-axis labeled in a way that is confusing: Cox (GI thickness A). Capacitance isn’t measured in Angstroms, and GI thickness is a variable of Cox. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim (US 20160233253 A1).
Regarding Claim 1, Kim teaches a display panel (see display device in Fig. 1) comprising
a plurality of sub-pixels (displays are comprises of these units), each sub-pixel having a driving thin-film transistor (see driving TFT T1 in Fig. 2 and [0054]), a switching thin-film transistor (see switching TFT T2 in Fig. 2 and [0054]), and a storage capacitor (see storage capacitor Cst in Fig. 1 and [0052]) on a substrate (see substrate 100 in Fig. 3 and [0050])
the driving thin-film transistor (T1) includes:
a semiconductor layer (see semiconductor layer Act1 in Fig. 2; [0063]) comprising a source region and a drain region (SA/DA)
a gate electrode (g1) overlapping the semiconductor layer
a source electrode and a drain electrode electrically connected to the source region and the drain region (s1/d1 and [0069]) and
a gate insulating layer (GI) located between the semiconductor layer and the gate electrode (see Figs. 2 or 3 and [0064]), and
wherein the semiconductor layer is a dehydrogenated semiconductor layer ([0077] teaches that the mobility of the Act1 of driving TFT T1 may be modified because its "hydrogen ions spread to the outside" due to an annealing process).
Regarding Claim 7, Kim teaches that the semiconductor layer undergoes a heat treatment/annealing process ([0077]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20160233253 A1) in view of Tsai (US 20180350307 A1).
Regarding Claim 2, Kim teaches all the features as explained in the rejection of claim 1. However, Kim does not explicitly recite that the semiconductor layer has a mobility of 79 cm^2/Vs to 82 cm^2/Vs.
Nonetheless, it would have been obvious to a person of ordinary skill in the art to modify the device of Kim with the teachings of Tsai. Specifically, Tsai teaches that mobility is a constituent variable of the transconductance parameter (Kpn) used to stabilize driving current and reduce mura ([0035]). Since Kim teaches that the mobility of the semiconductor layer is specifically adjusted through an annealing/dehydrogenation process ([0077]), it would have been obvious to a PHOSITA to tune the thermal budget of the process in Kim to arrive at the specific mobility range of 79 cm^2/Vs to 82 cm^2/Vs to achieve the desired Kpn stability and mura reduction taught by Tsai. The selection of this specific narrow range is a matter of routine optimization of a known result-effective variable (mobility) to achieve the predictable result of uniform display brightness.
Regarding Claim 5, Kim teaches the structural arrangement as previously established, but do not explicitly use the term "K-factor." Nonetheless, Tsai is in the same or analogous field and explicitly defines the transistor transconductance parameter (Kpn, see [0035]). Tsai further teaches that variations in this parameter lead to "uneven brightness (mura)" ([0002]) and that the output current is directly determined by this parameter ([0036]). A person having ordinary skill in the art (PHOSITA) would have recognized that the structural modification suggested by Cho—making the gate insulating layer of the driving transistor DT thicker than that of the switching transistor SW ([0191])—necessarily results in a different Kpn for each device. Because gate capacitance (Cox) is inversely proportional to thickness, a PHOSITA would understand that increasing the thickness of the driving transistor's gate insulator (as taught by Cho) inherently reduces its Cox, thereby resulting in the driving thin-film transistor having a smaller Kpn than the switching thin-film transistor. The modification would have been obvious to a PHOSITA as a predictable means to reduce the sensitivity of the driving current to voltage variations, thereby solving the mura problem identified in both Tsai.
Regarding Claim 6, Kim teaches the driving transistor T1 is connected to a light-emitting element, but Tsai explicitly teaches that the sub-pixel includes an organic light-emitting diode (OLED) electrically connected to the drain electrode of the driving transistor (see [0002] and [0036]). It would have been obvious to a PHOSITA to utilize an OLED as the light-emitting element in Kim’s panel to achieve the high contrast and fast response times associated with OLED technology.
Claim 3, 4, 12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20160233253 A1) in view of Cho (US 20230065849 A1).
Regarding Claim 3, Kim teaches the basic sub-pixel structure but not the thickness difference.
However, Cho explicitly teaches that the equivalent oxide thickness of the gate insulating layer in the driving transistor DT may be larger than that of the switching transistor SW ([0191]). A person of ordinary skill in the art would have recognized that the greater the thickness of the gate insulating layer is, the stronger the driving capability of the driving transistor is; and the smaller the thickness of the gate insulating layer is, the stronger the switching control capability of the switching transistor is. Therefore, applying the thickness differentiation of Cho to the sub-pixel of Kim would be a predictable application of known structural variations to optimize individual transistor performance for their respective roles in the circuit.
Regarding Claim 4, Kim in view of Cho fails to explicitly recite the exact claimed ranges. However, Cho explicitly teaches overlapping and encompassing ranges for the gate insulating layers in paragraph [0191]. Specifically, Cho teaches that the thickness for switching transistors SW may range from 1,000 Å to 1,500 Å, and for driving transistors DT may range from 1,250 Å to 1,750 Å. The claimed range for the driving transistor (1500 Å to 1700 Å) is a sub-range entirely within the range taught by Cho. The claimed range for the switching transistor (1380 Å to 1580 Å) significantly overlaps with the range taught by Cho. Under MPEP 2144.05, a claimed range that is within or overlaps a prior art range is considered prima facie obvious. A PHOSITA would have found it obvious to select specific thicknesses within these known, functional ranges to optimize the driving sensitivity and switching speed of the respective transistors based on routine design choices.
Regarding Claim 12, the reasons for rejecting claims 1 and 3 are essentially the same.
Regarding Claims 14-15, the reasons for rejecting claims 3 and 4 are essentially the same.
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20160233253 A1) in view of Cho (US 20230065849 A1) and Tsai (US 20180350307 A1).
Regarding Claim 13, the reasons for rejecting claim 2 are essentially the same.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899