DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/21/2023 and 05/03/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Species B and Claims 1-8, 11-14, and 17-20 in the reply filed on 01/07/2026 is acknowledged. Claims 9-10 and 15-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/07/2026.
Claim Objections
Claim 1-8, 11-13, and 17-20 are objected to because of the following informalities:
Claims 1 - 7, 11 - 13, and 17 – 20 recite the phrases “first ones”, “second ones”, “third ones”, “fourth ones”, “fifth ones”, “sixth ones”, “seventh ones”, “eighth ones”, “ninth ones” and “tenth ones”; these phrases appear to be improper terms and the Examiner suggests improving these phrases with “first sets” to “tenth sets” or “first subsets” to “tenth subsets” or “first collections” to “tenth collections” or “first groups” to “tenth groups”.
Claim 8 recites “wherein the forming the second structure comprises forming pixels of an image sensor on the first wafer”; this should be written as “wherein the forming the second structure comprises forming pixels of an image sensor on the second wafer.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 7, 11 – 13, and 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220278074A1; hereinafter Chen) in view of Sutanrii et al. (JPH08186064A; hereinafter Sutanrii), further in view of Jones et al. (US20070023121A1; hereinafter Jones).
Regarding Claim 1, Chen discloses a method of manufacturing a semiconductor device (process of forming multi-die stacking structure, [0016]), the method comprising:
forming a first structure (device regions 110 and interconnect structure 130) on a first wafer (100), FIGS. 2, [0021];
forming a second structure (device region 210 and interconnect structure 230) on
a second wafer (200a) including second chip regions (dies 212) and a second scribe lane region (dicing lanes 211) surrounding the second chip regions (212), FIGS. 11 & 12, [0042];
Chen [0056] discloses bonding wafer 200a to wafer 100 such that bond pads 255 and bonding layer 250 of wafer 200 are aligned with vias 120 and bonding layer 160 of the wafer 100.
separating the bonded first (100) and second wafers (200a) by a third dicing process, FIG. 38a reproduced below, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
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Chen: FIG. 38a
Chen does not disclose “separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer.”
In a similar art, Sutanrii discloses a method for testing semiconductor devices and dicing semiconductor wafers [0002].
Sutanrii discloses: separating first ones of the second chip regions (semiconductor pellets 21) in a central portion (20) of the … wafer in a plan view by a first dicing process (isolation region 12 is cut to separate the central portion 20 and peripheral portion 30), FIG. 1A reproduced below, [0014], [0022].
separating second ones of the second chip regions (semiconductor pellets 31) in an edge portion (peripheral portion 30) of the … wafer in a plan view by a second dicing process (dicing along divided region 32), FIG. 3A, [0014], [0024];
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Sutanrii: FIG. 1(A)
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage, thereby improving manufacturability [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method in order to improve manufacturability as disclosed by Sutanrii [0011].
In a similar art, Jones discloses semiconductor fabrication using 3D integration [0001].
Jones discloses: bonding the first ones of the second chip regions (a panel 104) with the first wafer (200), FIG. 4 reproduced below, [0024].
bonding the second ones of the second chip regions (a panel 104) with the first wafer (200), FIG. 4, [0024].
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Jones: FIG. 4
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sutanrii’s method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 2, The combination of Chen, Sutanrii, and Jones discloses method of claim 1.
Chen discloses: wherein the first wafer (100) includes first chip regions (112) and a first scribe lane region (111) surrounding the first chip regions (112), FIG. 1, [0018] and
wherein the bonding the first ones of the second chip regions (a subset of dies 212 of wafer 200a) with the first wafer (100) comprises bonding the first wafer (100) and the second wafer (200a) such that the first ones of the second chip regions of the second wafer (a subset of dies 212 of wafer 200a) are aligned with corresponding ones of the first chip regions of the first wafer (a subset of dies 112 of wafer 100), FIG. 20a, [0056].
Chen [0056] discloses bonding wafer 200a to wafer 100 such that bond pads 255 and bonding layer 250 of wafer 200a are aligned with vias 120 and bonding layer 160 of the wafer 100, indicating the first ones of the second chip regions of the second wafer are aligned with corresponding ones of the first chip regions of the first wafer.
Regarding Claim 3, The combination of Chen, Sutanrii, and Jones disclose the method of claim 2.
Chen discloses: wherein the bonding the second ones of the second chip regions (a subset of dies 212 of wafer 200a) with the first wafer (100) comprises bonding the first (100) and second wafers (200a) such that the second ones of the second chip regions of the second wafer (a subset of dies 212 of wafer 200a) are aligned with corresponding ones of the first chip regions of the first wafer (a subset of dies 112 of wafer 100), FIG. 20a, [0056].
Chen [0056] discloses bonding wafer 200a to wafer 100 such that bond pads 255 and bonding layer 250 of wafer 200a are aligned with vias 120 and bonding layer 160 of the wafer 100, indicating bonding the first and second wafers such that the second ones of the second chip regions of the second wafer are aligned with corresponding ones of the first chip regions of the first wafer.
Regarding Claim 4, The combination of Chen, Sutanrii, and Jones disclose the method of claim 2.
Chen discloses: wherein the first structure (device regions 110 and interconnect structure 130) includes a first bonding pattern (via 120) and in each of the first chip regions (112), and the second structure (device region 210 and interconnect structure 230) includes a second bonding pattern (bond pads 255) in each of the second chip regions (212), [0056],
each of the first (device regions 110 and interconnect structure 130) and second structures (device region 210 and interconnect structure 230) including a metal (interconnect structures 130 and 230 include metal lines, [0023], [0045]), and
wherein the bonding the first ones of the second chip regions of the second wafer (a subset of dies 212 of wafer 200a) with the first wafer (100) comprises bonding the first (100) and second wafers (200a) such that the first (120) and second bonding patterns (255) contact each other, FIG. 20a, [0056].
Regarding Claim 5, The combination of Chen, Sutanrii, and Jones disclose the method of claim 4.
Chen discloses: wherein the bonding the second ones of the second chip regions of the second wafer (a subset of dies 212 of wafer 200a) with the first wafer (100) comprises bonding the first (100) and second (200a) wafers such that the first (120) and second bonding patterns (255) contact each other, FIG. 20a, [0056].
Regarding Claim 6, The combination of Chen, Sutanrii, and Jones discloses the method of claim 1.
Chen discloses: wherein the method further comprises:
the third dicing process, FIG. 38a, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “separating third ones of the second chip regions in a first edge portion of the second wafer in a plan view and bonding the third ones of the second chip regions with the first wafer; and separating, prior to the third dicing process, fourth ones of the second chip regions in a second edge portion of the second wafer in a plan view by a fourth dicing process and bonding the fourth ones of the second chip regions with the first wafer.”
Sutanrii discloses: separating third ones of the second chip regions in a first edge portion (a subset of peripheral portion 30) of the … wafer in a plan view, FIG. 1, [0024].
separating, prior to the third dicing process (Chen: [0082]), fourth ones of the second chip regions in a second edge portion (a subset of peripheral portion 30) of the … wafer in a plan view by a fourth dicing process (dicing along divided region 32), FIG. 3A, [0014], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage, thereby improving manufacturability [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to improve manufacturability as disclosed by Sutanrii [0011].
Jones discloses: bonding the third ones of the second chip regions (a panel 104) with the first wafer (200), FIG. 4, [0024] and
bonding the fourth ones of the second chip regions (a panel 104) with the first wafer (200), FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 7, The combination of Chen, Sutanrii, and Jones disclose the method of claim 1.
Chen discloses: wherein the method further comprises, prior to the third dicing process, FIG. 38a, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
forming a third structure on a third wafer (200b) including third chip regions (dies 212) and a third scribe lane region (dicing lanes 211) surrounding the third chip regions (dies 212), FIG. 25, [0065], [0066]. Chen discloses another wafer 200b is bonded to 200a and additional wafers 200 up to 200n may be stacked and bonded, indicating the wafers may be of the same type including third chip regions (212) and third scribe lane region (211) surrounding the third chip regions (212).
separating the bonded first (100) and second (200a) wafers by the third dicing process comprises separating the bonded first (100), second (200a) and third (200b) wafers, FIG. 38a, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “separating third ones of the third chip regions in a central portion of the third wafer in a plan view by a fourth dicing process; bonding the third ones of the third chip regions with the second wafer; separating fourth ones of the third chip regions in an edge portion of the third wafer in a plan view by a fifth dicing process; bonding the fourth ones of the third chip regions with the second wafer.”
Sutanrii discloses: separating third ones of the third chip regions in a central portion (Sutanrii: central portion 20) of the … wafer in a plan view by a fourth dicing process (central portion 20 is cut to form pellets 21 by further dicing processes), [0009];
separating fourth ones of the third chip regions in an edge portion (Sutanrii: peripheral portion 30) of the … wafer in a plan view by a fifth dicing process (peripheral portion 30 is cut to form pellets 31 by further dicing processes), [0009].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage, thereby improving manufacturability [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to improve manufacturability as disclosed by Sutanrii [0011].
Jones discloses: bonding the third ones of the third chip regions (a panel 104) with the second wafer (200), FIG. 4, [0024];
bonding the fourth ones of the third chip regions (a panel 104) with the second wafer (200), FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 11, Chen discloses a method of manufacturing a semiconductor device (process of forming multi-die stacking structure, [0016]), the method comprising:
Chen discloses: forming a first structure (device regions 110 and interconnect structure 130) on a first wafer (wafer 100) including first chip regions (dies 112), a first scribe lane region (dicing lanes 111) surrounding the first chip regions (dies 112), and a first bonding pattern (via 120) in each of the first chip regions (dies 112), the first bonding pattern including a metal (via 120 is formed of copper), FIG. 1, [0018], [0026].
forming a second structure (device region 210 and interconnect structure 230) on a second wafer (wafer 200a) including second chip regions (dies 212), a second scribe lane region (dicing lanes 211) surrounding the second chip regions (dies 212), and a second bonding pattern (bond pads 255) in each of the second chip regions (dies 212), the second bonding pattern including a metal (contact pads 255 include metals), FIG. 11, [0042], [0056].
second bonding pattern (255) contacts the first bonding pattern (120), (bonding patterns 255 and 120 contact each other, [0056]).
Chen [0056] discloses bonding wafer 200a to wafer 100 such that bond pads 255 and bonding layer 250 of wafer 200 are aligned with vias 120 and bonding layer 160 of the wafer 100.
separating the bonded first (100), second (200a) and third (200b) wafers by a dicing process, FIG. 38a, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer such that the second bonding pattern contacts the first bonding pattern; after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer.”
In a similar art, Sutanrii discloses a method for testing semiconductor devices and dicing semiconductor wafers [0002].
Sutanrii discloses: after separating second ones of the second chip regions in a first portion (central portion 20) of the … wafer, FIG. 1A, [0009], [0022].
after separating fourth ones of the second chip regions in a second portion (peripheral portion 30) of the … wafer, FIG. 3A, [0009], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
In a similar art, Jones discloses semiconductor fabrication using 3D integration [0001].
Jones discloses: bonding the second ones of the second chip regions (a panel 104) with corresponding first ones of the first chip regions (a panel site 204) of the first wafer (200), FIG. 4, [0024].
bonding the fourth ones of the second chip regions (a panel 104) with corresponding third ones of the first chip regions (a panel site 204) of the first wafer (200, FIG. 4), [0024].
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sutanrii’s method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 12, The combination of Chen, Sutanrii, and Jones discloses the method of claim 11.
Chen discloses: further comprising, prior to the dicing process, FIG. 38a, [0082].
Chen [0082] discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
second bonding pattern (255) contacts the first bonding pattern (120), (bonding patterns 255 and 120 contact each other, [0056]).
Chen [0056] discloses bonding wafer 200a to wafer 100 such that bond pads 255 and bonding layer 250 of wafer 200 are aligned with vias 120 and bonding layer 160 of the wafer 100.
Chen does not disclose “after separating sixth ones of the second chip regions in a third portion of the second wafer, bonding the sixth ones of the second chip regions with corresponding fifth ones of the first chip regions of the first wafer.”
Sutanrii discloses: after separating sixth ones of the second chip regions (peripheral portion 30) in a third portion of the … wafer, FIG. 1, [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
Jones discloses: bonding the sixth ones of the second chip regions (a panel 104) with corresponding fifth ones of the first chip regions (a panel site 204) of the first wafer (200).
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 13, The combination of Chen, Sutanrii, and Jones discloses the method of claim 11.
Chen discloses: further comprising, prior to the dicing process, FIG. 38a, [0082]. Chen [0082] discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
forming a third structure (device region 210 and interconnect structure 230) on a third wafer (200b) including third chip regions (212), a third scribe lane region (211) surrounding the third chip regions (212), and a third bonding pattern (255) in each of the third chip regions, the third bonding pattern (255) including a metal, (contact pads 255 include metals), FIG. 11, [0042], [0056].
the third bonding pattern (bond pads 255 on wafer 200b) contacts the second bonding pattern (bond pads 255 on wafer 200a through vias 220), [0056].
Chen [0065], [0066] discloses another wafer 200b is bonded to 200a and additional wafers 200 up to 200n may be stacked and bonded, indicating the wafers may be of the same type including third chip regions (212) and third scribe lane region (211) surrounding the third chip regions (212), and third bonding pattern (bond pads on wafer 200b), FIG. 25, [0063].
wherein the dicing process comprises separating the bonded first (100), second (200a) and third (200b) wafers FIG. 38a, [0082].
Chen does not disclose “after separating sixth ones of the third chip regions in a first portion of the third wafer, bonding the sixth ones of the third chip regions with corresponding fifth ones of the second chip regions of the second wafer; and after separating eighth ones of the third chip regions in a second portion of the third wafer, bonding the eighth ones of the third chip regions with corresponding seventh ones of the second chip regions of the second wafer.”
Sutanrii discloses: after separating sixth ones of the third chip regions (pellets 21) in a first portion (central portion 20) of the … wafer, FIG. 1A, [0014], [0022].
after separating eighth ones of the third chip regions (pellets 31) in a second portion (peripheral portion 30) of the … wafer, FIG. 3A, [0014], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
Jones discloses: bonding the sixth ones of the … chip regions (a panel 104) with corresponding fifth ones (a panel site 204) of the second chip regions of the second wafer (200).
bonding the eighth ones of the … chip regions (a panel 104) with corresponding seventh ones of the second chip regions (a panel site 204) of the second wafer (200).
Jones discloses that a method as taught enables selective bonding and improves manufacturability [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve manufacturability as disclosed by Jones [0014].
Regarding Claim 17, Chen discloses a method of manufacturing a semiconductor device (process of forming multi-die stacking structure, [0016]), the method comprising:
forming a first structure (device regions 110 and interconnect structure 130) on a first wafer (wafer 100) including first chip regions (dies 112) and a first scribe lane region (dicing lanes 111) surrounding the first chip regions (dies 112), FIG. 1, [0018], [0021];
forming a second structure (device region 210 and interconnect structure 230) on a second wafer (wafer 200a) including second chip regions (dies 212) and a second scribe lane region (dicing lanes 211) surrounding the second chip regions (dies 212), FIG. 11, 12, [0042];
forming a third structure on a third wafer (wafer 200b) including third chip regions (dies 212) and a third scribe lane region (dicing lanes 211) surrounding the third chip regions (dies 212), FIG. 25, [0065], [0066]. Chen discloses another wafer 200b is bonded to 200a and additional wafers 200 up to 200n may be stacked and bonded, indicating the third wafer 200b includes third chip regions (dies 212) and a third scribe lane region (dicing lanes 211) surrounding the third chip regions (dies 212).
separating the bonded first (100), second (200a) and third (200b) wafers by a dicing process, FIG. 38a, [0082]. Chen discloses the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “after separating second ones of the second chip regions in a first portion of the second wafer, bonding the second ones of the second chip regions with corresponding first ones of the first chip regions of the first wafer; after separating fourth ones of the second chip regions in a second portion of the second wafer, bonding the fourth ones of the second chip regions with corresponding third ones of the first chip regions of the first wafer; after separating sixth ones of the third chip regions in a first portion of the third wafer, bonding the sixth ones of the third chip regions with corresponding fifth ones of the second chip regions of the second wafer;
after separating eighth ones of the third chip regions in a second portion of the third wafer, bonding the eighth ones of the third chip regions with corresponding seventh ones of the second chip regions of the second wafer.”
In a similar art, Sutanrii discloses a method for testing semiconductor devices and dicing semiconductor wafers [0002].
Sutanrii discloses: after separating second ones of the second chip regions (semiconductor pellets 21) in a first portion (central portion 20) of the … wafer, FIG. 1A, [0009], [0022].
after separating fourth ones of the second chip regions (semiconductor pellets 31) in a second portion (peripheral portion 30) of the … wafer, FIG. 3A, [0009], [0024].
after separating sixth ones of the third chip regions (semiconductor pellets 21) in in a first portion (central portion 20) of the … wafer, FIG. 1A, [0009], [0022].
after separating eighth ones of the third chip regions (semiconductor pellets 31) in a second portion (peripheral portion 30) of the … wafer, FIG. 3A, [0009], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
In a similar art, Jones discloses semiconductor fabrication using 3D integration [0001].
Sutanrii [0009] discloses separation of central portion (20) and peripheral portion (30) of the semiconductor wafer by a dicing method first, and thereafter dividing the first semiconductor pellets 21 in the central portion 20 and the second semiconductor pellets 31 in the peripheral portion 30, and Jones [0024] discloses bonding of separated panels 104 to corresponding panel sites 204 of wafer 200.
Jones discloses: bonding the second ones of the second chip regions (a panel 104) with corresponding first ones of the first chip regions (a panel site 204) of the first wafer (200), FIG. 4, [0024].
bonding the fourth ones of the second chip regions (a panel 104) with corresponding third ones of the first chip regions (a panel site 204) of the first wafer (200), FIG. 4, [0024].
bonding the sixth ones of the third chip regions (a panel 104) with corresponding fifth ones of the second chip regions (a panel site 204) of the … wafer, FIG. 4, [0024];
bonding the eighth ones of the third chip regions (a panel 104) with corresponding seventh ones of the second chip regions (a panel site 204) of the … wafer, FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves yield [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sutanrii’s method in order to enable selective bonding and improve yield as disclosed by Jones [0014].
Regarding Claim 18, The combination of Chen, Sutanrii, and Jones discloses the method of claim 17.
Chen discloses: further comprising, prior to the dicing process, FIG. 38a, [0082].
Chen [0082] discloses a dicing process after bonding, where the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “after separating tenth ones of the second chip regions in a third portion of the second wafer, bonding the tenth ones of the second chip regions with corresponding ninth ones of the first chip regions of the first wafer.”
Sutanrii [0009] discloses separation of central portion (20) and peripheral portion (30) of the semiconductor wafer by a dicing method first, and thereafter dividing the first semiconductor pellets 21 in the central portion 20 and the second semiconductor pellets 31 in the peripheral portion 30, and Jones [0024] discloses bonding of separated panels 104 to corresponding panel sites 204 of wafer 200.
Sutanrii discloses: after separating tenth ones of the second chip regions (pellets 31) in a third portion (peripheral portion 30) of the … wafer, FIG. 3A, [0009], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
Jones discloses: bonding the tenth ones of the second chip regions (a panel 104) with corresponding ninth ones of the first chip regions (a panel site 204) of the first wafer (200), FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves yield [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve yield as disclosed by Jones [0014].
Regarding Claim 19, The combination of Chen, Sutanrii, and Jones discloses the method of claim 17.
Chen discloses: further comprising, prior to the dicing process, FIG. 38a, [0082].
Chen [0082] discloses a dicing process after bonding, where the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Chen does not disclose “after separating tenth ones of the third chip regions in a third portion of the third wafer, bonding the tenth ones of the third chip regions with corresponding ninth ones of the second chip regions of the second wafer.”
Sutanrii [0009] discloses separation of central portion (20) and peripheral portion (30) of the semiconductor wafer by a dicing method first, and thereafter dividing the first semiconductor pellets 21 in the central portion 20 and the second semiconductor pellets 31 in the peripheral portion 30, and Jones [0024] discloses bonding of separated panels 104 to corresponding panel sites 204 of wafer 200. Chen [0082] discloses a dicing process after bonding, where the package 500 which includes the bonded wafers 100, 200a, 200b is singulated by suitable cutting technique 560 such as sawing and plasma etch technique.
Sutanrii discloses: after separating tenth ones of the third chip regions (pellets 31) in a third portion (peripheral portion 30) of the … wafer, FIG. 3A, [0009], [0024].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
Jones discloses: bonding the tenth ones of the third chip regions (a panel 104) with corresponding ninth ones of the second chip regions (a panel site 204) of the second wafer (200), FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves yield [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve yield as disclosed by Jones [0014].
Regarding Claim 20, The combination of Chen, Sutanrii, and Jones discloses the method of claim 17.
Chen discloses: wherein the first structure (device regions 110 and interconnect structure 130) includes a first bonding pattern (via 120) in each of the first chip regions (112), and the second structure (device region 210 and interconnect structure 230) includes a second bonding pattern (255) in each of the second chip regions (212), each of the first and second bonding patterns including a metal (120 is formed of copper [0026] and contact pads 255 include metals [0056]), FIG. 1, [0056].
the first (100) and second wafers (200a) are bonded such that the first (120) and second (255) bonding patterns contact each other, [0056].
Chen does not disclose “wherein after separating the second ones of the second chip regions of the second wafer and bonding the second ones of the second chip regions with the corresponding first ones of the first chip regions of the first wafer.”
Sutanrii discloses: after separating second ones of the second chip regions (pellets 21) in a first portion (central portion 20) of the … wafer, FIG. 1A, [0009], [0022].
Sutanrii discloses that a method as taught enables separate processing of the central and peripheral portions of the wafer without damage [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable separate processing of the central and peripheral portions of the wafer without damage as disclosed by Sutanrii [0011].
Sutanrii [0009] discloses separation of central portion (20) and peripheral portion (30) of the semiconductor wafer by a dicing method first, and thereafter dividing the first semiconductor pellets 21 in the central portion 20 and the second semiconductor pellets 31 in the peripheral portion 30, and Jones [0024] discloses bonding of separated panels 104 to corresponding panel sites 204 of wafer 200.
Jones discloses: bonding the second ones of the second chip regions (panels 104) with corresponding first ones of the first chip regions (a panel site 204) of the first wafer (200), FIG. 4, [0024].
Jones discloses that a method as taught enables selective bonding and improves yield [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable selective bonding and improve yield as disclosed by Jones [0014].
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sutanrii, further in view of Jones, still further in view of Fan (US20140211056A1; hereinafter Fan).
Regarding Claim 8, The combination of Chen, Sutanrii, and Jones discloses the method of claim 7.
Chen discloses: wherein the forming the first structure (device regions 110 and interconnect structure 130) comprises forming elements (transistors 118) for converting electronic signals into voltage signals on the first wafer (100), [0021].
The combination of Chen, Sutanrii, and Jones does not disclose “wherein the forming the second structure comprises forming pixels of an image sensor on the first wafer, and wherein the forming the third structure comprises forming a logic device on the third wafer.”
In a similar art, Fan discloses a method of manufacturing the image sensor [0072].
Fan discloses: wherein the forming the second structure comprises forming pixels of an image sensor on the second wafer (pixels 136 including photodiodes 154, formed on photodiode chip 170 of the image sensor 130), FIG. 8, [0093], [0095] and
wherein the forming the third structure comprises forming a logic device on the third wafer (logic device formed on the periphery logic chip 174), FIG. 8, [0093].
Fan discloses that a method as taught enables image-sensor functionality of the wafers and improves device performance [0095]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen, Sutanrii, and Jones’ method in order to enable image-sensor functionality of the wafer and improves device performance as disclosed by Fan [0095].
Regarding Claim 14, The combination of Chen, Sutanrii, and Jones discloses the method of claim 13.
Chen discloses: wherein the forming the first structure (device regions 110 and interconnect structure 130) comprises forming elements (transistors 118) for converting electronic signals into voltage signals on the first wafer (100), [0021].
The combination of Chen, Sutanrii, and Jones does not disclose “wherein the forming the second structure comprises forming pixels of an image sensor on the first wafer, and wherein the forming the third structure comprises forming a logic device on the third wafer.”
Fan discloses: wherein the forming the second structure comprises forming pixels of an image sensor on the second wafer (pixels 136 including photodiodes 154, formed on photodiode chip 170 of the image sensor 130), FIG. 8, [0093], [0095] and
wherein the forming the third structure comprises forming a logic device on the third wafer (logic device formed on the periphery logic chip 174), FIG. 8, [0093].
Fan discloses that a method as taught enables image-sensor functionality of the wafers and improves device performance [0095]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen, Sutanrii, and Jones’ method in order to enable image-sensor functionality of the wafer and improves device performance as disclosed by Fan [0095].
Conclusion
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/Krishna J. Palaniswamy/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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