DETAILED ACTION
This office action is in response to applicant’s RCE filed on 06/04/2026.
Currently claims 1-7, 9-11, and 13-22 are pending in the application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 13 and 19 have been considered but are moot because the new grounds of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 11 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2015/0364422 A1 (Zhai).
Regarding claim 1, Zhai discloses, a semiconductor package (Figs. 6, 11; [0032] – [0039]) comprising:
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a redistribution line structure (118; redistribution layer; Fig. 6; [0032]) comprising a plurality of redistribution line patterns (120);
a first semiconductor chip (102) and a second semiconductor chip (104) on the redistribution line structure (118) and spaced apart from each other (Fig. 6; [0027]);
a bridge structure (112) between the first semiconductor chip (102), the second semiconductor chip (104), and the redistribution line structure (118), the bridge structure (112) comprising a plurality of connection wiring patterns (115) configured to electrically connect the first semiconductor chip (102) to the second semiconductor chip (104) (Fig. 6; [0029]); and
a molding layer (116; Fig. 6; [0030]) extending continuously (as evident in Fig. 6) around a sidewall of the bridge structure (112) and filled between the first semiconductor chip (102), the second semiconductor chip (104), and the redistribution line structure (118) and between the first semiconductor chip (102) and the second semiconductor chip (104) (Fig. 6; [0030]),
wherein lowermost surfaces of the plurality of connection wiring patterns (115) are above uppermost surfaces of the plurality of redistribution line patterns (118) (as evident in Fig. 6); and
wherein no redistribution line structure (118) is between the bridge structure (112) and the first semiconductor chip (102), or between the bridge structure (112) and the second semiconductor chip (104) (as evident in Fig. 6).
Regarding claim 2, Zhai discloses, the semiconductor package of claim 1, further comprising a connection pillar (114; terminals; Fig. 6; [0029]) configured to electrically connect the first semiconductor chip (102) to the bridge structure (112) and electrically connect the second semiconductor chip (104) to the bridge structure (112).
Regarding claim 3, Zhai discloses, the semiconductor package of claim 2, wherein the connection pillar (114; terminals; Fig. 6; [0029]) is in contact with the first semiconductor chip and the bridge structure and in contact with the second semiconductor chip and the bridge structure (terminals 114 on silicon bridge 112 electrically connect bridge to logic die 102 and memory die 104 simultaneously).
Regarding claim 4, Zhai discloses, the semiconductor package of claim 2, wherein the connection pillar (114) penetrates through the molding layer (116).
Regarding claim 11, Zhai discloses, the semiconductor package of claim 1, wherein the first semiconductor chip (102) comprises a first physical region (as annotated on Fig. 6) overlapping the bridge structure (112), wherein the second semiconductor chip (104) comprises a second physical region (as annotated on Fig. 6) overlapping the bridge structure (112), and wherein the first semiconductor chip (102) transmits and receives signals to and from the second semiconductor chip (104) through the first physical region and the second physical region (as annotated on Fig. 6).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0364422 A1 (Zhai) as applied to claim 2 and further in view of US 2020/0176384 A1 (Wu).
Regarding claim 5, Zhai fails to teach explicitly, the semiconductor package of claim 2, further comprising an adhesive layer between the first semiconductor chip, the second semiconductor chip, and the bridge structure, wherein the connection pillar penetrates through the adhesive layer.
However, in analogous art, Wu discloses, the semiconductor package of claim 2, further comprising an adhesive layer (130; protective layer; Fig. 1E; [0035]; Specification of instant application also calls it a protective film) between the first semiconductor chip (110), the second semiconductor chip (120), and the bridge structure (140), wherein the connection pillar (134) penetrates through the adhesive layer (130) (Fig. 1E; [0031], [0035]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai and Wu before him/her, to modify the teachings of a semiconductor package as taught by Zhai and to include the teachings of an adhesive/protective layer between the first semiconductor chip, the second semiconductor chip, and the bridge structure as taught by Wu since the protective layer would provide extra protection to both semiconductor chips and the bridge structure. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Wu while forming a semiconductor package of Zhai.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0364422 A1 (Zhai) as applied to claim 1 and further in view of US 2021/0193577 A1 (Lin).
Regarding claim 9, Zhai fails to teach explicitly, the semiconductor package of claim 1, wherein a minimum pitch of the plurality of connection wiring patterns is less than a minimum pitch of the plurality of redistribution line patterns.
However, in analogous art, Lin discloses, the semiconductor package of claim 1, wherein a minimum pitch of the plurality of connection wiring patterns is less than a minimum pitch of the plurality of redistribution line patterns (Fig. 1J; [0052]; Lin teaches that the pitch of the traces of the RDL structure 50 is larger than the pitch of the metal lines included in the interconnection structure of the bridge die 36).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai and Lin before him/her, to modify the teachings of a semiconductor package as taught by Zhai and to include the teachings of relative pitch of connection wiring patterns and redistribution line patterns as taught by Lin since in MPEP2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Lin while forming a semiconductor package of Zhai.
Regarding claim 10, Zhai fails to teach explicitly, the semiconductor package of claim 1, wherein a minimum width of the plurality of connection wiring patterns is less than a minimum width of the plurality of redistribution line patterns.
However, in analogous art, Lin discloses, the semiconductor package of claim 1, wherein a minimum width of the plurality of connection wiring patterns is less than a minimum width of the plurality of redistribution line patterns (Fig. 1J; [0052]; Fig. 1J shows that thickness or width of RDL is higher than that of bridge structure). See MPEP 2125 (1) where it states that Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai and Lin before him/her, to modify the teachings of a semiconductor package as taught by Zhai and to include the teachings of minimum width of the plurality of connection wiring patterns is less than a minimum width of the plurality of redistribution line patterns as taught by Lin since in MPEP2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Lin while forming a semiconductor package of Zhai.
Claims 13-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0364422 A1 (Zhai) and further in view of US 2021/0134728 A1 (Rubin).
Regarding claim 13, Zhai discloses, a semiconductor package (Figs. 6, 11; [0032] – [0039]) comprising:
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a molding layer (116; Fig. 6; [0030]) having a first surface and a second surface opposite to the first surface (as annotated on Fig. 6), the molding layer (116) extending continuously between the first surface and the second surface, and comprising a first trench and a second trench on the first surface and a third trench on the second surface (as annotated on Fig. 6);
a redistribution line structure (118; redistribution layer; Fig. 6; [0032]) on the second surface of the molding layer (116);
a first semiconductor chip (102) in the first trench (Fig. 6; [0027]);
a second semiconductor chip (104) in the second trench (Fig. 6; [0027]);
a bridge structure (112) in the third trench (as annotated on Fig. 6; [0027]; and
wherein no redistribution line structure (118) is between the bridge structure (112) and the first semiconductor chip (102), or between the bridge structure (112) and the second semiconductor chip (104) (as evident in Fig. 6).
But Zhai fails to teach explicitly, a first pillar, in the molding layer, configured to electrically connect the first semiconductor chip to the redistribution line structure; a second pillar, in the molding layer, configured to electrically connect the second semiconductor chip to the redistribution line structure; a connection pillar, in the molding layer, in contact with the first semiconductor chip and the bridge structure and in contact with the second semiconductor chip and the bridge structure;
However, in analogous art, Rubin discloses, a first pillar (614, as annotated on Fig. 6B; metallic pillar; [0082]), in the molding layer (612; insulating layer equivalent to molding layer; Fig. 6B; [0082]), configured to electrically connect the first semiconductor chip (140; IC chip; Fig. 6B; [0082]) to the redistribution line structure (620; redistribution line structure; Fig. 6B; [0082]);
a second pillar (614, as annotated on Fig. 6B; metallic pillar; [0082]), in the molding layer (612), configured to electrically connect the second semiconductor chip (150; IC chip; Fig. 6B; [0082]) to the redistribution line structure (620);
a connection pillar (144/154, as annotated on Fig. 6B; interconnects; [0082]), in the molding layer (612), in contact with the first semiconductor chip (140) and the bridge structure (110; interconnect bridge; Fig. 6B; [0082]) and in contact with the second semiconductor chip (150) and the bridge structure (110);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai and Rubin before him/her, to modify the teachings of a semiconductor package with bridge structure as taught by Zhai and to include the teachings various metallic pillars and bumps to make connection between IC chips and bridge structures as taught by Rubin since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Rubin while forming a semiconductor package of Zhai.
Regarding claim 14, the combination of Zhai and Rubin discloses, the semiconductor package of claim 13, wherein the first pillar, the second pillar, and the connection pillar comprise a same material (copper; [0055]; Rubin Ref.).
Regarding claim 15, Zhai discloses, the semiconductor package of claim 13, wherein the redistribution line structure (118) comprises a plurality of redistribution line patterns, wherein the bridge structure (112) comprises a plurality of connection wiring patterns (as evident in Fig. 6), and wherein the plurality of redistribution line patterns are not in contact with the plurality of connection wiring patterns (bridge 112 (with traces 115) sits above, separate from RDL 118 (routing 120). No physical contact between bridge traces and RDL routing; FIG. 6).
Regarding claim 18, the combination of Zhai and Rubin discloses, the semiconductor package of claim 13, wherein the first pillar (as annotated on Fig. 6B) is in contact with the first semiconductor chip (140) and the redistribution line structure (620), and wherein the second pillar (as annotated on Fig. 6B) is in contact with the second semiconductor chip (150) and the redistribution line structure (620) (Rubin Ref.).
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Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhai and Rubin as applied to claim 13 and further in view of US 2020/0176384 A1 (Wu).
Regarding claim 16, the combination of Zhai and Rubin fails to teach explicitly, the semiconductor package of claim 13, further comprising a protective film surrounding the connection pillar.
However, in analogous art, Wu discloses, the semiconductor package of claim 13, further comprising a protective film (130; protective layer; Fig. 1E; [0035]) surrounding the connection pillar (134).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai, Rubin and Wu before him/her, to modify the teachings of a semiconductor package as taught by Zhai and to include the teachings of protective film surrounding the connection pillar as taught by Wu since the protective layer would provide extra protection to both semiconductor chips, the bridge structure and the pillars. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Wu while forming a semiconductor package of Zhai.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20150364422 A1 (Zhai).
Note: The examiner used a single reference USC 103 Rejection due to the use of MPEP 2144.04 (VI) (B).
Regarding claim 19, Zhai discloses, a semiconductor package (Figs. 6, 11; [0032] – [0039]) comprising:
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a redistribution line structure (118; redistribution layer; Fig. 6; [0032]);
a first semiconductor chip (102) on the redistribution line structure (118);
a second semiconductor chip (104) on one side of the first semiconductor chip (102) on the redistribution line structure (118);
a third semiconductor chip (duplicate chip, see MPEP 2144.04 (VI) (B) – duplication of parts; placing a third chip on the opposite side of the first (center) chip is a straightforward, predictable extension — there is no structural or functional reason that limits the concept to two chips) on another side of the first semiconductor chip (102) on the redistribution line structure (118);
a first bridge structure (112), in a first region (just below the first and second IC chips) between the redistribution line structure (118), the first semiconductor chip (102), and the second semiconductor chip (104), configured to electrically connect the first semiconductor chip (102) to the second semiconductor chip (104);
a second bridge structure (see MPEP 2144.04 (VI) (B) – duplication of parts; adding a second bridge to connect additional chips is a straightforward, predictable extension — there is no structural or functional reason that limits the concept), in a second region (just below the first and duplicate IC chips) between the redistribution line structure (RDL), the first semiconductor chip (102), and the third semiconductor chip (duplicate chip), configured to electrically connect the first semiconductor chip (102) to the third semiconductor chip (duplicate chip); and
a molding layer (116; Fig. 6; [0030]) on the redistribution line structure (118) and extending continuously in the first region and the second region, and between adjacent ones of the first semiconductor chip (102), the second semiconductor chip (104), and the third semiconductor chip (duplicate), wherein the first bridge structure and the second bridge structure are insulated from the redistribution line structure (insulated region in between), and
wherein no redistribution line structure (118) is between the bridge structure (112) and the first semiconductor chip (102), or between the bridge structure (112) and the second semiconductor chip (104) (as evident in Fig. 6).
Regarding claim 20, Zhai discloses, the semiconductor package of claim 19, wherein the first semiconductor chip (102) comprises a logic semiconductor chip, and wherein the second semiconductor chip (104) and the third semiconductor chip (duplicate die) comprise memory semiconductor chips (Fig. 6; [0034]).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 20150364422 A1 (Zhai) as applied to claim 19 and further in view of US 2020/0161266 A1 (Shim).
Regarding claim 21, Zhai fails to teach explicitly, the semiconductor package of claim 19, further comprising: a fourth semiconductor chip on the one side of the first semiconductor chip on the redistribution line structure; a fifth semiconductor chip on the other side of the first semiconductor chip on the redistribution line structure; a third bridge structure, in a third region between the redistribution line structure, the first semiconductor chip, and the fourth semiconductor chip, configured to electrically connect the first semiconductor chip to the fourth semiconductor chip; and a fourth bridge structure, in a fourth region between the redistribution line structure, the first semiconductor chip, and the fifth semiconductor chip, configured to electrically connect the first semiconductor chip to the fifth semiconductor chip, wherein the third bridge structure and the fourth bridge structure are insulated from the redistribution line structure.
However, in analogous art, Shim discloses, a third semiconductor chip on another side of the first semiconductor chip on the redistribution line structure (as annotated on Fig. 6; [0043] – [0046]);
a second bridge structure (as annotated on Fig. 6), in a second region between the redistribution line structure, the first semiconductor chip, and the third semiconductor chip, configured to electrically connect the first semiconductor chip to the third semiconductor chip (as shown in Fig. 6; [0043] – [0046]); and
a molding layer (130 and 141; encapsulant and second insulating layer; Fig. 6; [0044], [0047]), on the redistribution line structure, configured to be filled in the second region, and between adjacent ones of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip (as shown in Fig. 6; [0043] – [0047]),
wherein the second bridge structure (150, right, as annotated on Fig. 6; [0043]) is insulated (by insulating layer 141) from the redistribution line structure (as annotated on Fig. 6).
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With the above teaching, it is well within the purview of a person with ordinary skill in the art to extend the concept to five chips with four bridges. Applies the same bridge-chip connectivity pattern in all four cardinal directions around a central chip. Each additional chip/bridge pair is an identical replication of the basic two-chip/one-bridge unit of Zhai. However, Shim showed an example of such an embodiment in Fig. 7.
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Shim further teaches, the semiconductor package of claim 19, further comprising: a fourth semiconductor chip on the one side of the first semiconductor chip on the redistribution line structure (as annotated on Fig. 7; [0053] – [0056]; Shim reference);
a fifth semiconductor chip on the other side of the first semiconductor chip on the redistribution line structure (as annotated on Fig. 7; [0053] – [0056]; Shim reference);
a third bridge structure, in a third region (where the third bridge is) between the redistribution line structure, the first semiconductor chip, and the fourth semiconductor chip, configured to electrically connect the first semiconductor chip to the fourth semiconductor chip (as annotated on Fig. 7; [0053] – [0056], [0061]; Shim reference); and
a fourth bridge structure, in a fourth region (where the fourth bridge is) between the redistribution line structure, the first semiconductor chip, and the fifth semiconductor chip, configured to electrically connect the first semiconductor chip to the fifth semiconductor chip (as annotated on Fig. 7; [0053] – [0056], [0061; Shim reference),
Note: The examiner considered here that the bridge 150 is separated between second and fourth chips and between third and fifth chips. In MPEP 2144.04 (V) (C), it is stated that The court held that "if it were considered desirable for any reason to obtain access to the end of [the prior art’s] holder to which the cap is applied, it would be obvious to make the cap removable for that purpose." In the instant case, if forming individual bridges for second-fifth chips facilitate the connections, then having separate bridges for each of them would be obvious.
wherein the third bridge structure and the fourth bridge structure are insulated (by the resistance of substrate 431; Fig. 1J; [0029]) from the redistribution line structure (as annotated on Fig. 7; [0053] – [0056], [0061; Shim reference).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Zhai and Shim before him/her, to modify the teachings of a semiconductor package having two chips connected by a bridge as taught by Zhai and to include the teachings of a semiconductor package having three chips connected by two bridges as taught by Shim since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Zhai, a person with ordinary skill in the art would be motivated to reach out to Shim while forming a semiconductor package of Zhai.
Regarding claim 22, the combination of Zhai and Shim discloses, the semiconductor package of claim 19, further comprising:
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a fourth semiconductor chip disposed on the one side of the first semiconductor chip on the redistribution line structure (as annotated on Fig. 7; [0053] – [0056]; Shim reference); and
a fifth semiconductor chip disposed on the other side of the first semiconductor chip on the redistribution line structure (as annotated on Fig. 7; [0053] – [0056]; Shim reference),
wherein the first bridge structure is configured to electrically connect the first semiconductor chip to the fourth semiconductor chip and the second bridge structure is configured to electrically connect the first semiconductor chip to the fifth semiconductor chip (as annotated on Fig. 7; [0053] – [0056]; Shim reference).
Allowable Subject Matter
Claims 6-7 and 17 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2015/0364422 A1 (Zhai), in combination with US 2021/0134728 A1 (Rubin), US 2020/0176384 A1 (Wu), US 2021/0193577 A1 (Lin) and US 2020/0161266 A1 (Shim), in combination with the other claimed features, fails to disclose, “the semiconductor package of claim 1, further comprising a dummy chip on the first semiconductor chip, wherein an upper surface of the dummy chip is coplanar with an upper surface of the second semiconductor chip and an upper surface of the molding layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor package of claim 1, further comprising a dummy chip on the first semiconductor chip, wherein an upper surface of the dummy chip is coplanar with an upper surface of the second semiconductor chip and an upper surface of the molding layer,’ is material to the inventive concept of the application at hand to avoid direct overlap/contact with the redistribution layer by providing a bridge wiring above the redistribution wiring and helps integrate the chips without an interposer. This arrangement is presented as improving reliability and signal path length.
Regarding claim 17, the closest prior art, US 2015/0364422 A1 (Zhai), in combination with US 2021/0134728 A1 (Rubin), US 2020/0176384 A1 (Wu), US 2021/0193577 A1 (Lin) and US 2020/0161266 A1 (Shim), in combination with the other claimed features, fails to disclose, “the semiconductor package of claim 13, further comprising a dummy chip on the first semiconductor chip, wherein the first surface of the molding layer is coplanar with an upper surface of the dummy chip and with an upper surface of the second semiconductor chip”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor package of claim 13, further comprising a dummy chip on the first semiconductor chip, wherein the first surface of the molding layer is coplanar with an upper surface of the dummy chip and with an upper surface of the second semiconductor chip,’ is material to the inventive concept of the application at hand to avoid direct overlap/contact with the redistribution layer by providing a bridge wiring above the redistribution wiring and helps integrate the chips without an interposer. This arrangement is presented as improving reliability and signal path length.
Claim 7 is also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0148940 A1 (Chen) - A structure is disclosed including a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
US 2021/0118758 A1 (Cheng) - Semiconductor packages are disclosed. A semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.
US 2021/0074645 A1 (Tsai) - A chip package structure is disclosed using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.
US 2019/0109117 A1 (Fang) - A semiconductor device package is disclosed including a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
06/26/2026
Prosecution Insights