Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Applicant has stated in the claim 1 that the display panel is configured to modulate exposure of the transistor active layers to light and/or hydrogen. However, according to the applicant’s specification this functional limitation is achieved by overlapping the gate electrode over the source and the drain region. Therefore, the panel by itself does not have this feature.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun (US Pub No. 20190051245), in view of Honda et al (us Pub No. 20110260160).
With respect to claim 1, Jun discloses a data signal line supplying a data signal (DL,Fig.2); a scan signal line supplying a scan signal (Scan1); and a first transistor disposed in a subpixel where the data signal line and the scan signal line are connected (T1). However, Jun does not explicitly disclose the first transistor comprising, a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to another side of the first active layer, and a first gate electrode overlapping with the first active layer, overlapping with at least a portion of the first source electrode, and overlapping with at least a portion of the first drain electrode; and display panel configured to modulate exposure of transistor active layers to light and/or hydrogen in order to improve display panel performance, the display panel. On the other hand, Honda et al discloses a first active layer (bottom white strip layer,Fig.4A), a first source electrode (304a or b) connected to one side of the first active layer (Fig.4A), a first drain electrode (304 a or b) connected to another side of the first active layer (Fig.4A), and a first gate electrode (307) overlapping with the first active layer (Fig.4E), overlapping with at least a portion of the first source electrode (Fig.4E), and overlapping with at least a portion of the first drain electrode (Fig.4E); as far as the functional limitations “ display panel configured to modulate exposure of transistor active layers to light and/or hydrogen in order to improve display panel performance, the display panel” are shown by Honda et al since the gate electrode overlaps source and drain electrodes according to Honda et al which is in accordance with applicant’s specification. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Jun according to the teachings of the Honda et al such that source and drain electrodes along with gate electrodes are formed and the gate electrode overlaps source and drain and the channel regions, in order to make a thin film transistor to be used for display devices.
Claim(s) 2,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun (US Pub No. 20190051245), in view of Honda et al (us Pub No. 20110260160), in view of Kim et al (US Pub No. 20200052057).
With respect to claim 2, the arts cited above do not explicitly disclose further comprising a light emitting element, a second transistor, and a storage capacitor disposed in the subpixel, wherein the light emitting element comprises a first electrode, an emission layer, and a second electrode, and wherein the second transistor comprises: a second active layer; a second source electrode connected to one side of the second active layer; a second drain electrode connected to another side of the second active layer; and a second gate electrode overlapping with a portion of the second active layer, and not overlapping with the second source electrode and the second drain electrode. On the other hand, Kim et al discloses a light emitting element (140,Fig.5), a second transistor (110), and a storage capacitor disposed in the subpixel (C1), wherein the light emitting element comprises a first electrode (141), an emission layer (142), and a second electrode (143), and wherein the second transistor comprises: a second active layer (111); a second source electrode (113) connected to one side of the second active layer (Fig.5); a second drain electrode (114) connected to another side of the second active layer (Fig.5); and a second gate electrode overlapping with a portion of the second active layer (112), and not overlapping with the second source electrode (Fig.5) and the second drain electrode (Fig.5). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Kim et al such that a light emitting element, a second transistor, and a storage capacitor disposed in the subpixel, wherein the light emitting element comprises a first electrode, an emission layer, and a second electrode, and wherein the second transistor comprises: a second active layer; a second source electrode connected to one side of the second active layer; a second drain electrode connected to another side of the second active layer; and a second gate electrode overlapping with a portion of the second active layer, and not overlapping with the second source electrode and the second drain electrode, in order to make a driver for the light emitting portion, so the display can be controlled and programmed.
With respect to claim 18, Kim et al discloses further comprising an additional storage capacitor formed by overlapping between the first source electrode and the first gate electrode (because naturally there is capacitance between source and the gate electrode since they overlap and there is dielectric layer between them, Fig.5).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun (US Pub No. 20190051245), in view of Honda et al (us Pub No. 20110260160), in view of Kim et al (US Pub No. 20200052057), in view of Watanabe et al (US Patent No. 8575610).
With respect to claim 17, the arts cited above do not explicitly disclose wherein an overlapping area between the first source electrode and the first gate electrode is greater than an overlapping area between the first drain electrode and the first gate electrode. On the other hand, Watanabe et al discloses wherein an overlapping area (between 108 and 102a,Fig.3D) between the first source electrode (102a) and the first gate electrode (108) is greater than an overlapping area between the first drain electrode (102b) and the first gate electrode. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Watanabe et al such that an overlapping area between the first source electrode and the first gate electrode is greater than an overlapping area between the first drain electrode and the first gate electrode, to alleviate an electric field in the device.
Allowable Subject Matter
Claims 3-16 are allowed.
Response to Arguments
Applicant's arguments filed on 05/04/2026 have been fully considered but they are not persuasive. The new amendment to claim 1 is functional limitation which is the result of the structure disclosed by Honda et al, which is in accordance with applicant’s specification. Regarding applicant’s argument against claim 2 rejection, the gate electrode does not overlap with the source or drain electrodes as shown in Fig.5 in Kim et al. Regarding applicant’s argument against claim 18, there is always cross talk capacitance between neighboring electrodes or wires separated by thin dielectric material. Regarding applicant’s argument against claim 17 rejection, previous prior arts such as Hinda et al show the overlap between gate electrode and the drain electrode, Watanabe et al was used to show that overlap with source electrode can be greater than the drain electrode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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