Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on August 22, 2023, July 17, 2024, November 27, 2024, & March 9, 2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species II (claims 1-7, 9, 11-20) in the reply filed on 12/13/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, & 11-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Armitage et al. (Pub. No.: US 2019/0393379 A1).
Regarding Claim 1, Armitage et al. discloses
an all-nitride-based epitaxial and chip structure, comprising: an N-type semiconductor layer (302 (Fig. 4F – upper first epitaxial layer) or 310 (Fig. 3 – second epitaxial layer)), a P-type semiconductor layer (208), an electroluminescent (EL) multiple quantum wells (MQWs) region (210 (Figs. 3 & 4F)/214 (Fig. 2C), and a first photoluminescent (PL) multiple quantum wells (MQWs) region (206) stacked on a main surface
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of a substrate (202), wherein the N-type semiconductor layer (302/310) and the P-type semiconductor layer (208) are disposed on two sides of the EL MQWs region (210/214) respectively (Par. 0038-0040, 0053-0054, 0057-0075; Fig. 4F together with Figs. 2C & 3); holes from the P-type semiconductor layer (208) and electrons from the N-type semiconductor layer (302/310) recombine in the EL MQWs region (210/214), generating first-color light by an EL method (Par. 0053-0054, 0057-0075; Fig. 4F together with Figs. 2C & 3); the first-color light is further transmitted to the first PL MQWs region (206) where second-color light is generated by a PL method (Par. 0053-0054, 0057-0075; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 2, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, further comprising a P-type electrode (402) , wherein the P-type electrode is disposed on a side of the P-type semiconductor layer (208) away from the EL MQWs region (210/214) (Par. 0078-0088; Fig. 4F together with Figs. 2C & 3); the P-type electrode (402) is a reflective electrode with/without a conductive reflection layer underneath (Par. 0078-0088; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 3, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, wherein the holes from the P-type semiconductor layer are configured not to reach the first PL MQWs region (Par. 0061; Fig. 4F together with Figs. 2C & 3. - implied).
Regarding Claim 4, Armitage et al., as applied to claim 3, discloses
the epitaxial and chip structure, wherein the thickness of the EL MQWs region is configured in a way that holes from the P-type semiconductor layer cannot reach the first PL MQWs region (Par. 0061; Fig. 4F together with Figs. 2C & 3. - implied).
Regarding Claim 5, Armitage et al., as applied to claim 3, discloses
the epitaxial and chip structure, comprising a separation layer (204) disposed between the EL MQWs region (210/214) and the first PL MQWs region (206), wherein the separation layer is configured to block the holes from the P-type semiconductor layer from reaching the first PL MQWs region (Par. 0061; Fig. 4F together with Figs. 2C & 3. - implied).
Regarding Claim 6, Armitage et al., as applied to claim 5, discloses
the epitaxial and chip structure, wherein the separation layer is an N-type semiconductor material (Par. 0061; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 7, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, wherein the EL MQWs region (210/214) and the first PL MQWs region (206) are sandwiched between the N-type semiconductor layer (302/310) and the P-type semiconductor layer (208) (Par. 0053-0054, 0057-0075; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 9, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, wherein the EL MQWs region (210/214) and the first PL MQWs region (206) comprises quantum wells of InGaN or InGaAlN respectively; the In content in the quantum wells of the EL MQWs region is less than that of the first PL MQWs region (Par. 0058-0060; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 11, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, further comprising a spectral-reflection enhancement structure (304), wherein the spectral-reflection enhancement structure is disposed on a side of the first PL MQWs region (206) away from the EL MQWs region (210/214); the spectral- reflection enhancement structure (304) is configured to reflect the first-color light that is not absorbed by the first PL MQWs region back into the first PL MQWs region, and meantime to allow the second- color light to pass through the spectral-reflection enhancement structure (Par. 0067; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 12, Armitage et al., as applied to claim 1, discloses
the epitaxial and chip structure, wherein the first PL MQWs region is configured to convert a portion of the first-color light into the second-color light; and the second-color light is further mixed with the remaining portion of the first-color light forming a third-color light (Par. 0058-0067; Fig. 4F together with Figs. 2C & 3).
Regarding Claim 13, Armitage et al., as applied to claim 2, discloses
the epitaxial and chip structure, further comprising a second PL MQWs region (212), wherein the first-color light and/or the second-color light is/are transmitted to the second PL MQWs region, generating the third-color light by the PL method; the reflective electrode or the conductive reflection layer is configured to reflect the second-color light and/or the third-color light (Par. 0058-0067; Fig. 2C - third color light, for example, is a red color light; second color light, for example, is a green color light; and first color light, for example, is a blue color light).
Regarding Claim 14, Armitage et al., as applied to claim 13, discloses the epitaxial and chip structure, wherein the second PL MQWs region (212) and the first PL MQWs region (206) are disposed on a side of the EL MQWs region (214); or the second PL MQWs region and the first PL MQWs region are disposed on the two sides of the EL MQWs region respectively (Fig. 2C).
Regarding Claim 15, Armitage et al., as applied to claim 14, discloses the epitaxial and chip structure, wherein wavelengths of the first-color light are in a range of 360nm-460nm (Par. 0058-0067; Fig. 2C).
Regarding Claim 16, Armitage et al., as applied to claim 14, discloses the epitaxial and chip structure, wherein the wavelengths of the first-color light are in a range of 360nm-420nm, and wavelengths of the second-color light are in a range of 420nm-480nm; or the wavelengths of the first-color light are in a range of 420nm-480nm, and the wavelengths of the second-color light are in a range of 490nm-550nm; or the wavelengths of the first-color light are in a range of 490nm-550nm, and the wavelengths of the second-color light are in a range of 560nm-650nm . (Par. 0058-0067; Fig. 2C).
Regarding Claim 17, Armitage et al., as applied to claim 1, discloses the epitaxial and chip structure, comprising a normal face- up structure, a flip-chip structure, a vertical chip structure, or a thin film structure with the substrate removed (Par. 0094; Fig. 4F).
Regarding Claim 18, Armitage et al., as applied to claim 1, discloses the epitaxial and chip structure, further comprising a N- type electrode (406), wherein the N-type electrode is disposed on a side of the N-type semiconductor layer (302/310) away from the substrate (202) (Par. 0080; Fig. 4F and/or 6A).
Regarding Claim 19, Armitage et al., as applied to claim 1, discloses the epitaxial and chip structure, wherein the spectral- reflection enhancement structure is made of a reflector or a reflective film (Par. 0067).
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (Pub. No.: US 2017/0018679 A1).
Regarding Claim 20, Lee discloses
a light-emitting device, comprising an epitaxial and chip structure comprising: an N-type semiconductor layer (612b), a P-type semiconductor layer (612a), an EL MQWs region (112e), and a PL MQWs region (112p) stacked on a main surface of a substrate (SUB) (Par. 0038-0041, 0062-0063; Fig. 6); wherein the N-type semiconductor layer and the P-type semiconductor layer are disposed on two sides of the EL MQWs region respectively (Par. 0038, 0062-0063; Fig. 6);
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holes from the P-type semiconductor layer and electrons from the N-type semiconductor layer recombine in the EL MQWs region, generating first- color light by an EL method (Par. 0038, 0062-0063; Fig. 6); the first-color light is further transmitted to the first PL MQWs region where second-color light is generated by a PL method (Par. 0038, 0062-0063; Fig. 6); and a phosphor (Par. 0038, 0062-0063; Fig. 6 – phosphor 112f); wherein the phosphor is disposed on a light-emitting surface of the epitaxial and chip structure (Fig. 6); the first-color light and/or the second-color light are transmitted to the phosphor where another color light is generated (Par. 0038, 0062-0063; Fig. 6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugawara et al. (Pub. No.: US 2002/0139984 A1) – This prior art teaches an all-nitride-based epitaxial and chip structure, comprising: an N-type semiconductor layer (405), a P-type semiconductor layer (408), an electroluminescent (EL)
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region (406), and a first photoluminescent (PL) 404), wherein the N-type semiconductor layer (405) and the P-type semiconductor layer (408) are disposed on two sides of the EL406) respectively; holes from the P-type semiconductor layer and electrons from the N-type semiconductor layer recombine in the EL 404) where second-color light is generated by a PL method (Par. 0094; Fig. 7).
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01/13/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893