DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1 and 12 filed on 12/07/2025 have been fully considered for examination based on their merits. The previously presented claims 2-11, and 13-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-13, filed 12/07/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LI.
Regarding Claim 1. The Applicant stated (Remarks, pages 7-8), that the Amended claim 1 has two part features. The part (1) of the amended feature, recites, “the second doped portion is in direct contact with the first channel portion” according to claim 1 amendment. The part (2) of the amended feature, recites, “a length of the first doped portion in greater than that of the second doped portion” is considered. It is also noted that the Applicant included some of the claim 1 limitations (previous rejected by the prior art) such as “doping concentrations relations of doped portions” with the aforementioned part (1) amended feature. The Examiner in this Office Action only considered and rejected the claim 1 amended limitations based on the new grounds made in view of LI.
The Applicant argues that none of the prior art, CHEN1, CHEN2 and SAITO teaches the technical amended features of Claim 1. The Examiner agrees that the arguments with respect to the amended claim 1 features of part (1) and part (2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LI.
Li teaches an array substrate ([0002]) comprising: wherein the first transistor (Fig. 1-6, thin film transistor, [0091]) comprises: a length of the first doped portion (Fig. 13, 212, second doped portion) is greater (annotated Figure 13) than that of the second doped portion (Fig. 13, 211, first doped portion), and the second doped portion (Fig. 13, 211, first doped portion) is in direct contact (annotated Figure 13, [0070]) with the first channel portion (Fig. 13, 220, channel layer).
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Regarding Claims 2-20. The independent Claim(s) 12, and dependent claims 2-11, and 13-20 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yen-Hao Chen et al, (hereinafter CHEN1) US 20230187559 A1, in view of Pei-Ming Chen, (hereinafter CHEN2), US 20170301701 A1, in further view of Masaki Saitoh, (hereinafter SAITOH), US 20140099766 A1, and further in view of Zhifu Li et al, (hereinafter LI), CN 115425090 A.
Regarding Claim 1, CHEN1 teaches in Figure 1B, an array substrate (Fig. 1B, 10, semiconductor device), comprising:
a substrate (Fig. 1B, SB); and
a first transistor (Fig. 1B, 220/230, first semiconductor layer/second gate) disposed on the substrate;
wherein the first transistor comprises:
a first active layer (Fig. 1B, 220, first semiconductor layer) disposed on the substrate, and the first active layer comprises a first channel portion (Fig. 1B, 224, first channel region), a first doped portion (Fig. 1B, 222, first source region) and a second doped portion (Fig. 1B, 226, first drain region).
a first gate disposed (Fig. 1B, 230, second gate) on one side of the first active layer, and the first gate overlaps with the first channel portion (annotated Figure 1B); and
a source (Fig. 1B, 262, source) and a drain (Fig. 1B, 264, drain).
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CHEN1 does not explicitly disclose an array substrate comprising: the first doped portion and the second doped portion are connected to opposite ends of the first channel portion, respectively;
the first doped portion comprises a first doped sub-portion and a second doped sub-portion, and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion; a doping concentration of ions in the second doped sub-portion is less than a doping concentration of ions in the first doped sub-portion, the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion;
the source is connected to the second doped portion and the drain connected to the first doped sub-portion of the first doped portion.
CHEN2 teaches in Figure 7, an array substrate (Fig. 7, 30, active device) comprising:
the first doped portion (annotated Figure 7) and the second doped portion (annotated Figure 7) are connected to opposite ends of the first channel portion, respectively (annotated Figure 7);
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the first doped portion (annotated Figure 7) comprises a first doped sub-portion (Fig. 7, HD2, second heavily doped region) and a second doped sub-portion (Fig. 7, LD2, second lightly doped region), and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion (annotated Figure 7);
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a doping concentration of ions in the second doped sub-portion (annotated Figure 7, LD2) is less than (doping concentrations of the lightly doped regions (e.g. LD2), are less than that of the heavily doped regions (e.g. HD2), [0024]) a doping concentration of ions in the first doped sub-portion (annotated Figure 7, HD2).
the source (Fig. 7, 371, first electrode; Fig. 1G, 171, the first electrode may be a source electrode, [0020]) is connected to the second doped portion and the drain (Fig. 7, 372, second electrode; Fig. 1G, 172, the second electrode may be a drain electrode, [0020]) connected to the first doped sub-portion of the first doped portion (annotated Figure 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHEN1 to incorporate the teachings of CHEN2, such that an array substrate comprising: the first doped portion and the second doped portion are connected to opposite ends of the first channel portion, respectively; the first doped portion comprises a first doped sub-portion and a second doped sub-portion, and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion; a doping concentration of ions in the second doped sub-portion is less than a doping concentration of ions in the first doped sub-portion, the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion; the source is connected to the second doped portion and the drain connected to the first doped sub-portion of the first doped portion. The said arrangement resulted in an active device wherein the two types semiconductor layers share a gate electrode, so as to improve space utilization of the active device. More specifically, in a display region of a display panel, an aperture ratio is increased, and an effect of a narrow frame may be further achieved and has relatively high electron mobility as well as relatively preferred low leakage current and the critical voltage (CHEN2, [0009]).
CHEN1 as modified by CHEN2 does not explicitly disclose an array substrate comprising: the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion.
SAITOH teaches an array substrate (Fig. 1, single LDD structure n-type TFT, [0108]) comprising: the doping concentration of ions in the first doped sub-portion (Fig. 9, 13nd, n-type high-concentration impurity region, [0113]; annotated Figure 9) is the same (an n-type high-concentration impurity region 13ns functioning as a source region is formed on one side of the channel region, 13c, and an n-type high-concentration impurity region, 13nd functioning as a drain region is formed on the other side of the channel region, 13c, [0004], [0113-0114]) as a doping concentration of ions in the second doped portion (Fig. 9, 13ns, n-type high-concentration impurity region, [0113]; annotated Figure 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEN1 as modified by CHEN2 to incorporate the teachings of SAITOH such that an array substrate comprising: the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion, so that to create respective high-concentration impurity regions that function as a source and drain region and further uses LDD structure, in manufacturing single offset structure TFTs for alleviating the electrical field in the drain region that prevents the characteristic deterioration due to hot carriers (SAITOH, [0004], [0426]).
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CHEN1 as modified by CHEN2 and SAITOH does not explicitly disclose an array substrate comprising: wherein the first transistor comprises: a length of the first doped portion is greater than that of the second doped portion, and the second doped portion is in direct contact with the first channel portion.
Li teaches an array substrate ([0002]) comprising: wherein the first transistor (Fig. 1-6, thin film transistor, [0091]) comprises: a length of the first doped portion (Fig. 13, 212, second doped portion) is greater (annotated Figure 13) than that of the second doped portion (Fig. 13, 211, first doped portion), and the second doped portion (Fig. 13, 211, first doped portion) is in direct contact (annotated Figure 13, [0070]) with the first channel portion (Fig. 13, 220, channel layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEN1 as modified by CHEN2 SAITOH and to incorporate the teachings of LI, such that an array substrate comprising: wherein the first transistor comprises: a length of the first doped portion is greater than that of the second doped portion, and the second doped portion is in direct contact with the first channel portion, so that when the charge carriers are transported between the channel layer (220) and the second doped portion (212), they must pass through the first doped portion (211), thereby achieving the effect of extending the channel length of the “channel region” and reducing leakage current (LI, [0070]).
Regarding Claim 2, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 1.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the first gate (Fig. 1B, 230, second gate) is disposed on one side of the first active layer (Fig. 1B, 220, first semiconductor layer) away from the substrate (annotated Figure 1B);
the array substrate further comprises a second transistor (Fig. 1B, 240/250, second semiconductor layer/second gate) disposed, and the second transistor comprises:
a second active layer (Fig. 1B, 240, second semiconductor layer), at least part of the second active layer is disposed on one side of the first gate away from the substrate (annotated Figure 1B); the second active layer comprises a second channel portion (Fig. 1B, 244, second channel region), a third doped portion (Fig. 1B, 246, second drain region), and a fourth doped portion (Fig. 1B, 242, second source region);
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the third doped portion and the fourth doped portion are connected to opposite ends of the second channel portion, respectively (annotated Figure 1B);
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the second channel portion overlaps with the first channel portion (Fig. 1B, 224, first channel region; annotated Figure 1B) and the second doped portion (Fig. 1B, 226, first drain region),
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the third doped portion overlaps with the second doped portion (annotated Figure 1B), and the fourth doped portion overlaps with the first doped portion (annotated Figure 1B); and
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a second gate, the second gate (Fig. 1B, 250, third gate) is disposed on one side of the second active layer away from the substrate and overlaps with the second channel portion (annotated Figure 1B).
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Regarding Claim 3, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 2.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the first transistor (Fig. 1B, 220/230, first semiconductor layer/second gate) is connected in parallel (annotated Figure 1B) with the second transistor (Fig. 1B, 240/250, second semiconductor layer/second gate).
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Regarding Claim 4, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 2.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a first insulating layer (Fig. 3B, 132, the second nitride layer) disposed between the first gate (Fig. 3B, 230, second gate) and the second active layer (Fig. 3B, 240, second semiconductor layer), wherein the third doped portion (Fig. 3B, 246, second drain region) is connected to the second doped portion (Fig. 3B, 226, first drain region) through a first via (Fig. 3B, CH2, second contact hole) penetrating through the first insulating layer (annotated Figure 3B).
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Regarding Claim 5, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 2.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a second insulating layer (Fig. 3B, 140, fourth gate dielectric layer) disposed between the second active layer (Fig. 3B, 240, second semiconductor layer) and the second gate (Fig. 3B, 250, third gate), and a third insulating layer (Fig. 3B, 150, the protective layer) covering the second gate, wherein the source (Fig. 3B, 262/264, source/drain) is disposed on the third insulating layer, and the source is connected to the third doped portion (Fig. 3B, 246, second drain region) through a second via (Fig. 3B, CH4, fourth contact hole) penetrating through the second insulating layer and the third insulating layer (annotated Figure 3B).
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Regarding Claim 6, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 5.
CHEN2 further teaches in Figure 7, an array substrate (Fig. 7, 30, active device) according to claim 5, wherein the drain (Fig. 4, 272, second electrode) is disposed on the third insulating layer (Figs. 3F/4, 280/260, an etch stop layer, 280 is disposed on the oxide semiconductor layer, 260, [0022]), and the drain is connected to the first doped sub-portion (Figs, 4/5B/5C, DP2/321/HD2; annotated Figures 5/5B-5C), through a third via (Fig. 4, TH1, a first through hole) penetrating through the first insulating layer (Fig. 4, 230), the second insulating layer (Fig. 4, 250) and the third insulating layer (Figs. 3F/4, 280/260, an etch stop layer, 280 is disposed on the oxide semiconductor layer, 260, [0022]).
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Regarding Claim 7 CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 6.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the fourth doped portion (Fig. 3B, 242, second source region) is connected to the first doped portion (Fig. 3B, 222, first source region) through a fourth via (Fig. 3B, CH1, first contact hole) penetrating (annotated Figure 3B) through the first insulating layer (Fig. 3B, 132, second nitride layer).
CHEN2 further teaches in Figure 7, the array substrate (Fig. 7, 30, active device), wherein the first doped portion (annotated Figure 7) comprises first doped sub-portion (Fig. 7, HD2).
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Regarding Claim 8, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 6.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a fifth via (Fig. 1B, fourth contact hole) penetrating (annotated Figure 1B) through the second insulating layer (Fig. 1B, 140, fourth gate dielectric layer) and the third insulating layer (Fig. 1B, 150, the protective layer), wherein the drain (Fig. 3B, 262/264, source/drain) is connected to the fourth doped portion (Fig. 1B, 246, second drain region) through the fifth via (annotated Figure 1B).
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Regarding Claim 9, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 2.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein a thickness ([0030]) of the second active layer (Fig. 1B, 240, second semiconductor layer) is less than that of the first active layer (Fig. 1B, 220, first semiconductor layer).
Regarding Claim 10, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 3.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a second insulating layer (Fig. 3B, 140, fourth gate dielectric layer) disposed between the second active layer (Fig. 3B, 240, second semiconductor layer) and the second gate (Fig. 3B, 250, third gate), and a third insulating layer (Fig. 3B, 150, the protective layer) covering the second gate, wherein the source (Fig. 3B, 262/264, source/drain) is disposed on the third insulating layer, and the source is connected to the third doped portion (Fig. 3B, 246, second drain region) through a second via penetrating (annotated Figure 3B) through the second insulating layer and the third insulating layer.
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Regarding Claim 11, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 4.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a second insulating layer (Fig. 3B, 140, fourth gate dielectric layer) disposed between the second active layer (Fig. 3B, 240, second semiconductor layer) and the second gate (Fig. 3B, 250, third gate), and a third insulating layer (Fig. 3B, 150, the protective layer) covering the second gate, wherein the source (Fig. 3B, 262/264, source/drain) is disposed on the third insulating layer, and the source is connected to the third doped portion (Fig. 3B, 246, second drain region) through a second via penetrating (annotated Figure 3B) through the second insulating layer and the third insulating layer.
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Regarding Claim 12, CHEN1 teaches in Figure 1B, an array substrate (Fig. 1B, 10, semiconductor device), comprising:
a substrate (Fig. 1B, SB); and
a first transistor (Fig. 1B, 220/230, first semiconductor layer/second gate) disposed on the substrate;
and wherein the first transistor comprises:
a first active layer (Fig. 1B, 220, first semiconductor layer) disposed on the substrate, and the first active layer comprises a first channel portion (Fig. 1B, 224, first channel region), a first doped portion (Fig. 1B, 222, first source region) and a second doped portion (Fig. 1B, 226, first drain region);
a first gate disposed (Fig. 1B, 230, second gate) on one side of the first active layer, and the first gate overlaps with the first channel portion (annotated Figure 1B); and
a source (Fig. 1B, 262, source) and a drain (Fig. 1B, 264, drain).
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CHEN1 does not explicitly disclose an array substrate comprising: the first doped portion and the second doped portion are connected to opposite ends of the first channel portion, respectively;
the first doped portion comprises a first doped sub-portion and a second doped sub-portion, and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion; a doping concentration of ions in the second doped sub-portion is less than a doping concentration of ions in the first doped sub-portion, the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion;
the source is connected to the second doped portion and the drain connected to the first doped sub-portion of the first doped portion.
CHEN2 teaches in Figure 7, an array substrate (Fig. 7, 30, active device) comprising:
the first doped portion (annotated Figure 7) and the second doped portion (annotated Figure 7) are connected to opposite ends of the first channel portion, respectively (annotated Figure 7);
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the first doped portion (annotated Figure 7) comprises a first doped sub-portion (Fig. 7, HD2, second heavily doped region) and a second doped sub-portion (Fig. 7, LD2, second lightly doped region), and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion (annotated Figure 7);
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a doping concentration of ions in the second doped sub-portion (annotated Figure 7, LD2) is less than (doping concentrations of the lightly doped regions (e.g. LD2), are less than that of the heavily doped regions (e.g. HD2), [0024]) a doping concentration of ions in the first doped sub-portion (annotated Figure 7, HD2).
the source (Fig. 7, 371, first electrode; Fig. 1G, 171, the first electrode may be a source electrode, [0020]) is connected to the second doped portion and the drain (Fig. 7, 372, second electrode; Fig. 1G, 172, the second electrode may be a drain electrode, [0020]) connected to the first doped sub-portion of the first doped portion (annotated Figure 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHEN1 to incorporate the teachings of CHEN2, such that an array substrate comprising: the first doped portion and the second doped portion are connected to opposite ends of the first channel portion, respectively; the first doped portion comprises a first doped sub-portion and a second doped sub-portion, and the second doped sub-portion is connected between the first channel portion and the first doped sub-portion; a doping concentration of ions in the second doped sub-portion is less than a doping concentration of ions in the first doped sub-portion, the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion; the source is connected to the second doped portion and the drain connected to the first doped sub-portion of the first doped portion. The said arrangement resulted in an active device wherein the two types semiconductor layers share a gate electrode, so as to improve space utilization of the active device. More specifically, in a display region of a display panel, an aperture ratio is increased, and an effect of a narrow frame may be further achieved and has relatively high electron mobility as well as relatively preferred low leakage current and the critical voltage (CHEN2, [0009]).
CHEN1 as modified by CHEN2 does not explicitly disclose an array substrate comprising: the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion.
SAITOH teaches an array substrate (Fig. 1, single LDD structure n-type TFT, [0108]) comprising: the doping concentration of ions in the first doped sub-portion (Fig. 9, 13nd, n-type high-concentration impurity region, [0113]; annotated Figure 9) is the same (an n-type high-concentration impurity region 13ns functioning as a source region is formed on one side of the channel region, 13c, and an n-type high-concentration impurity region, 13nd functioning as a drain region is formed on the other side of the channel region, 13c, [0004], [0113-0114]) as a doping concentration of ions in the second doped portion (Fig. 9, 13ns, n-type high-concentration impurity region, [0113]; annotated Figure 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEN1 as modified by CHEN2 to incorporate the teachings of SAITOH such that an array substrate comprising: the doping concentration of ions in the first doped sub-portion is the same as a doping concentration of ions in the second doped portion, so that to create respective high-concentration impurity regions that function as a source and drain region and further uses LDD structure, in manufacturing single offset structure TFTs for alleviating the electrical field in the drain region that prevents the characteristic deterioration due to hot carriers (SAITOH, [0004], [0426]).
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CHEN1 as modified by CHEN2 and SAITOH does not explicitly disclose an array substrate comprising: wherein the first transistor comprises: a length of the first doped portion is greater than that of the second doped portion, and the second doped portion is in direct contact with the first channel portion.
Li teaches an array substrate ([0002]) comprising: wherein the first transistor (Fig. 1-6, thin film transistor, [0091]) comprises: a length of the first doped portion (Fig. 13, 212, second doped portion) is greater (annotated Figure 13) than that of the second doped portion (Fig. 13, 211, first doped portion), and the second doped portion (Fig. 13, 211, first doped portion) is in direct contact (annotated Figure 13, [0070]) with the first channel portion (Fig. 13, 220, channel layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEN1 as modified by CHEN2 SAITOH and to incorporate the teachings of LI, such that an array substrate comprising: wherein the first transistor comprises: a length of the first doped portion is greater than that of the second doped portion, and the second doped portion is in direct contact with the first channel portion, so that when the charge carriers are transported between the channel layer (220) and the second doped portion (212), they must pass through the first doped portion (211), thereby achieving the effect of extending the channel length of the “channel region” and reducing leakage current (LI, [0070]).
Regarding Claim 13, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 12.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the first gate (Fig. 1B, 230, second gate) is disposed on one side of the first active layer (Fig. 1B, 220, first semiconductor layer) away from the substrate (annotated Figure 1B);
the array substrate further comprises a second transistor (Fig. 1B, 240/250, second semiconductor layer/second gate) disposed, and the second transistor comprises:
a second active layer (Fig. 1B, 240, second semiconductor layer), at least part of the second active layer is disposed on one side of the first gate away from the substrate (annotated Figure 1B); the second active layer comprises a second channel portion (Fig. 1B, 244, second channel region), a third doped portion (Fig. 1B, 246, second drain region), and a fourth doped portion (Fig. 1B, 242, second source region);
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the third doped portion and the fourth doped portion are connected to opposite ends of the second channel portion, respectively (annotated Figure 1B);
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the second channel portion overlaps with the first channel portion (Fig. 1B, 224, first channel region; annotated Figure 1B) and the second doped portion (Fig. 1B, 226, first drain region),
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the third doped portion overlaps with the second doped portion (annotated Figure 1B), and the fourth doped portion overlaps with the first doped portion (annotated Figure 1B); and
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a second gate, the second gate (Fig. 1B, 250, third gate) is disposed on one side of the second active layer away from the substrate and overlaps with the second channel portion (annotated Figure 1B).
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Regarding Claim 14, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 13.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the first transistor (Fig. 1B, 220/230, first semiconductor layer/second gate) is connected in parallel (annotated Figure 1B) with the second transistor (Fig. 1B, 240/250, second semiconductor layer/second gate).
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Regarding Claim 15, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 13.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a first insulating layer (Fig. 3B, 132, the second nitride layer) disposed between the first gate (Fig. 3B, 230, second gate) and the second active layer (Fig. 3B, 240, second semiconductor layer), wherein the third doped portion (Fig. 3B, 246, second drain region) is connected to the second doped portion (Fig. 3B, 226, first drain region) through a first via (Fig. 3B, CH2, second contact hole) penetrating through the first insulating layer (annotated Figure 3B).
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Regarding Claim 16, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 13.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a second insulating layer (Fig. 3B, 140, fourth gate dielectric layer) disposed between the second active layer (Fig. 3B, 240, second semiconductor layer) and the second gate (Fig. 3B, 250, third gate), and a third insulating layer (Fig. 3B, 150, the protective layer) covering the second gate, wherein the source (Fig. 3B, 262/264, source/drain) is disposed on the third insulating layer, and the source is connected to the third doped portion (Fig. 3B, 246, second drain region) through a second via penetrating (annotated Figure 3B) through the second insulating layer and the third insulating layer.
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761
882
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Greyscale
Regarding Claim 17, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 16.
CHEN2 further teaches in Figure 7, the display panel (Fig. 7, 30, active device), wherein the drain (Fig. 4, 272, second electrode) is disposed on the third insulating layer (Figs. 3F/4, 280/260, an etch stop layer, 280 is disposed on the oxide semiconductor layer, 260, [0022]), and the drain is connected to the first doped sub-portion (Figs, 4/5B/5C, DP2/321/HD2; annotated Figures 5/5B-5C), through a third via (Fig. 4, TH1, a first through hole) penetrating through the first insulating layer (Fig. 4, 230), the second insulating layer (Fig. 4, 250) and the third insulating layer (Figs. 3F/4, 280/260, an etch stop layer, 280 is disposed on the oxide semiconductor layer, 260, [0022]).
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790
941
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Greyscale
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797
1045
media_image16.png
Greyscale
Regarding Claim 18 CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 17.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein the fourth doped portion (Fig. 3B, 242, second source region) is connected to the first doped portion (Fig. 3B, 222, first source region) through a fourth via (Fig. 3B, CH1, first contact hole) penetrating (annotated Figure 3B) through the first insulating layer (Fig. 3B, 132, second nitride layer).
CHEN2 further teaches in Figure 7, the display panel (Fig. 7, 30, active device), wherein the first doped portion (annotated Figure 7) comprises first doped sub-portion (Fig. 7, HD2).
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651
842
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Greyscale
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870
1069
media_image18.png
Greyscale
Regarding Claim 19, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 17.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), further comprising a fifth via (Fig. 1B, fourth contact hole) penetrating (annotated Figure 1B) through the second insulating layer (Fig. 1B, 140, fourth gate dielectric layer) and the third insulating layer (Fig. 1B, 150, the protective layer), wherein the drain (Fig. 3B, 262/264, source/drain) is connected to the fourth doped portion (Fig. 1B, 246, second drain region) through the fifth via (annotated Figure 1B).
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709
882
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Greyscale
Regarding Claim 20, CHEN1 as modified by CHEN2, SAITOH, and LI teaches the array substrate according to claim 13.
CHEN1 further teaches the array substrate (Fig. 1B, 10, semiconductor device), wherein a thickness ([0030]) of the second active layer (Fig. 1B, 240, second semiconductor layer) is less than that of the first active layer (Fig. 1B, 220, first semiconductor layer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230061581 A1 – Figure 6
STATEMENT OF RELEVANCE – The cross-sectional view of transistors, may include a first active layer, a first gate electrode, a second active layer, and a second gate electrode.
US 20220123120 A1 – Figure 8
STATEMENT OF RELEVANCE – The cross-sectional view illustrating a thin film transistor structure in the electronic device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812