DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For instance, the claimed limitations of “ the second lower electrode comprises titanium nitride ( SiN ) ” is undetermined because titanium nitride is not ( SiN ) /( silicon nitride). Rather, it is TiN . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8 and 12-17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Park et al. (US 2013/0009226 A1 hereinafter referred to as “Park”) . With respect to claim 1 , Park discloses, in Figs.1-27, a semiconductor device comprising: a substrate (100) comprising an active area; a first landing pad (140) connected to the active area and disposed on the substrate (100) ; a second landing pad (120a) connected to the active area, and spaced apart from the first landing pad (140) , wherein the second landing pad (120a) is disposed on the substrate (100) ; a first lower electrode (142) disposed on the first landing pad (140) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (142) disposed on the second landing pad (120a) and extending in the direction substantially perpendicular to the substrate (100) (see Par.[0069]-[0070] wherein active regions having an isolated (or, island) shape may be formed in the cell region of the substrate 100; a first pad contact 140 having a penetrating shape into the first capping insulating layer 114 and the first mask pattern 106a and making a contact with a first pad region in the active region; a gate electrode of the planar-type MOS transistor may include a polysilicon layer pattern 120a, a metal pattern 142 and a hard mask pattern 144 integrated one by one; bit line structures 145 (including a metal pattern 142 and a hard mask pattern 144) electrically connected with the first pad contact 140 may be also provided) ; a dielectric layer (1 14 ) extending along the first lower electrode (142) and the second lower electrode (142) (see Par.[0075]-[0076] wherein t he first mask pattern 106a may include silicon oxide ; see Par.[0095]-[0096] wherein t he first capping insulating layer 114 may be formed using a material having an etching selectivity with respect to the first mask pattern 106a. Particularly, the first capping insulating layer 114 may be formed by depositing silicon nitride ) ; and an upper electrode (150, 148, 134a) disposed on the dielectric layer (106a) , wherein a first upper surface of the first landing pad (140) is disposed below a second upper surface of the second landing pad (120a) with respect to a lower surface of the substrate (100) (see Par.[0078]-[0081] wherein a storage node contact 148 and the capacitor 150 may be provided on the second pad contacts 134a and 134b ) . With respect to claim 2 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a first lower surface of the first lower electrode (142) is disposed below a second lower surface of the second lower electrode (142) with respect to the lower surface of the substrate (see, for example, Fig.6A) . With respect to claim 3 , Park discloses, in Figs.1-27, t he semiconductor device, wherein the first lower electrode (142) has a first width at a first point and has a second width, which is greater than the first width, at a second point, wherein the second point is disposed above the first point with respect to the lower surface of the substrate (see, for example, Fig.6A wherein bit line metal pattern 142 over landing pad 140 has upper region width larger than the lower region width are shown ) . With respect to claim 4 , Park discloses, in Figs.1-27, t he semiconductor device, further comprising an insulating pattern (106a) disposed between the first landing pad (140) and the second landing pad (120a) , wherein an upper surface of the insulating pattern (106a) is disposed below the upper surface of the first landing pad (140) with respect to the lower surface of the substrate (100) (see Par.[0075]-[0076] wherein the first mask pattern 106a may include silicon oxide; see Par.[0095]-[0096] wherein the first capping insulating layer 114 may be formed using a material having an etching selectivity with respect to the first mask pattern 106a. Particularly, the first capping insulating layer 114 may be formed by depositing silicon nitride). With respect to claim 5 , Park discloses, in Figs.1-27, t he semiconductor device, wherein the dielectric layer (114) extends along the upper surface of the insulating pattern (106a) (see Par.[0075]-[0076] wherein the first mask pattern 106a may include silicon oxide; see Par.[0095]-[0096] wherein the first capping insulating layer 114 may be formed using a material having an etching selectivity with respect to the first mask pattern 106a ; p articularly, the first capping insulating layer 114 may be formed by depositing silicon nitride). With respect to claim 6 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a lowermost surface of the dielectric layer (114) is disposed below each of the upper surface of the first landing pad (140) and the upper surface of the second landing pad (120a) with respect to on the lower surface of the substrate (100) (see F ig.6A wherein the lower surface in cell region of insulating 114 extends pass pads 140 and 120a to penetrates the substrate active regions ) . With respect to claim 7 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a lower surface of the upper electrode (150, 148, 134) is disposed below the upper surface of the second landing pad (120a) with respect to the lower surface of the substrate (100) (see Fig.6A) . With respect to claim 8 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a first material /(polysilicon) included in each of the first landing pad (140) and the second landing pad (120a) is different from a second material /(metal) included in each of the first lower electrode (1420 and the second lower electrode (142) (see Par.[0077] wherein t he first pad contact 140 may include a conductive material (e.g., an impurity doped polysilicon) ; see Par.[0125] wherein t he gate electrode 147 may have an integrated shape of the polysilicon pattern 120a, the metal pattern 142 ) . With respect to claim 12 , Park discloses, in Figs.1-27, a semiconductor device comprising: a substrate (100) comprising an active area; a first landing pad (140) connected to the active area and disposed on the substrate (100) ; a second landing pad (120a) connected to the active area, and spaced apart from the first landing pad (140) , wherein the second landing pad (120a) is disposed on the substrate (100) ; an insulating pattern (1 06a ) disposed between the first landing pad (140) and the second landing pad (120a) ; a first lower electrode (142) disposed on the first landing pad (140) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (142) disposed on the second landing pad (120a) and extending in the direction substantially perpendicular to the substrate (100) ; a dielectric layer ( 114 ) extending along the first lower electrode (142) and the second lower electrode (142) ; and an upper electrode (150, 148, 134) disposed on the dielectric layer (114) , wherein the first landing pad (140) and the second landing pad (120a) protrude above an upper surface of the insulating pattern (1 06a ) with respect to a lower surface of the substrate (100) , and the dielectric layer ( 114 ) extends along portions of side surfaces of the first landing pad (140) and the second landing pad (120a) that protrude above the upper surface of the insulating pattern (106a) (see Par.[0069]-[0070] wherein active regions having an isolated (or, island) shape may be formed in the cell region of the substrate 100; a first pad contact 140 having a penetrating shape into the first capping insulating layer 114 and the first mask pattern 106a and making a contact with a first pad region in the active region; a gate electrode of the planar-type MOS transistor may include a polysilicon layer pattern 120a, a metal pattern 142 and a hard mask pattern 144 integrated one by one; bit line structures 145 (including a metal pattern 142 and a hard mask pattern 144) electrically connected with the first pad contact 140 may be also provided ; see Par.[0075]-[0076] wherein the first mask pattern 106a may include silicon oxide; see Par.[0095]-[0096] wherein the first capping insulating layer 114 may be formed using a material having an etching selectivity with respect to the first mask pattern 106a. Particularly, the first capping insulating layer 114 may be formed by depositing silicon nitride ; see Par.[0078]-[0081] wherein a storage node contact 148 and the capacitor 150 may be provided on the second pad contacts 134a and 134b ; a n insulating interlayer 146 may be provided between the storage node contact 148 and the capacitor 150 ). With respect to claim 13 , Park discloses, in Figs.1-27, t he semiconductor device, wherein the dielectric layer ( 114 ) extends along the upper surface of the insulating pattern (106a) . With respect to claim 14 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a first lower surface of the first lower electrode (142) is disposed below a second lower surface of the second lower electrode (120a) with respect to the lower surface of the substrate (see, for example, Fig.6A). With respect to claim 15 , Park discloses, in Figs.1-27, t he semiconductor device, wherein the first lower electrode comprises: a first portion /(lowest portion) disposed below an upper surface of the second landing pad (120a) ; and a second portion /(upper portion) disposed above the upper surface of the second landing pad (120a) and disposed on the first portion, wherein a width of the first portion is smaller than a portion of the second portion (see, for example, Fig.6A wherein bit line metal pattern 142 over landing pad 140 has upper region width larger than the lower region width are shown) . With respect to claim 16 , Park discloses, in Figs.1-27, t he semiconductor device, wherein an upper surface of the second landing pad (120a) is disposed above an upper surface of the first landing pad (140) with respect to the lower surface of the substrate (100) . With respect to claim 17 , Park discloses, in Figs.1-27, t he semiconductor device, wherein a lowermost surface of the dielectric layer (114) is disposed below each of a lower surface of the first lower electrode (142) and a lower surface of the second lower electrode (142) with respect to the lower surface of the substrate (100) (see Par.[0075]-[0076] wherein the first mask pattern 106a may include silicon oxide; see Par.[0095]-[0096] wherein the first capping insulating layer 114 may be formed using a material having an etching selectivity with respect to the first mask pattern 106a; particularly, the first capping insulating layer 114 may be formed by depositing silicon nitride). Claims 1-2, 7, 12-13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ho et al. (US 9,773,790 B1 hereinafter referred to as “Ho”) . With respect to claim 1 , Ho discloses, in Figs.1-6, a semiconductor device comprising: a substrate (100) comprising an active area (see col.3 lines 55-67, a plurality of shallow trench isolation (hereinafter abbreviated as STI) structures 106 are formed in the substrate 100 in the memory region 102 and the peripheral region 104 ) ; a first landing pad ( 140/152 ) connected to the active area and disposed on the substrate (100) ; a second landing pad (152) connected to the active area, and spaced apart from the first landing pad (140/150) , wherein the second landing pad (152) is disposed on the substrate (100) (see col.5 lines 15-60 wherein the first metal portions 150 include the metal layer 140 filling up the openings 122 and the second metal portion 152 include the metal layer 140 formed in the openings 122 and the landing pad 154 formed on the insulating layer 120, the first metal portions 150 and the second metal portions 152 include the same material but different heights and widths: a width of a top surface of the first metal portion 150 is smaller than a width of a top surface of the second metal portion 152, and a height H.sub.1 of the first metal portion 150 is smaller than a height H.sub.2 of the second metal portion 152 ) ; a first lower electrode (174) disposed on the first landing pad (150) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (172) disposed on the second landing pad (152) and extending in the direction substantially perpendicular to the substrate (100) (see col.6 -7, the first connecting structures 160 are electrically connected to the storage nodes 174 and the second connecting structures 162 are electrically connected to the storage nodes 172 ) ; a dielectric layer (126) extending along the first lower electrode (174) and the second lower electrode (172) (see col.5 lines 60-67 wherein an insulating layer 126 and a plurality of crown-like structures are formed on the substrate 100 in the memory region 102 ) ; and an upper electrode /(upper electrical connections between the storage nodes 172, 174) disposed on the dielectric layer, wherein a first upper surface of the first landing pad (150) is disposed below a second upper surface of the second landing pad (152) with respect to a lower surface of the substrate (100) (see col7, lines 40-67 wherein the connecting structures including the landing pads, electrical connections between the storage nodes and the memory cells are constructed ) . With respect to claim 2 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a first lower surface of the first lower electrode (174) is disposed below a second lower surface of the second lower electrode (172) with respect to the lower surface of the substrate (100) . With respect to claim 7 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a lower surface of the upper electrode is disposed below the upper surface of the second landing pad with respect to the lower surface of the substrate. With respect to claim 12 , Ho discloses, in Figs.1-6, a semiconductor device comprising: a substrate (100) comprising an active area (see col.3 lines 55-67, a plurality of shallow trench isolation (hereinafter abbreviated as STI) structures 106 are formed in the substrate 100 in the memory region 102 and the peripheral region 104) ; a first landing pad (150) connected to the active area and disposed on the substrate (100) ; a second landing pad (152) connected to the active area, and spaced apart from the first landing pad (150) , wherein the second landing pad (152) is disposed on the substrate (100) ; an insulating pattern disposed between the first landing pad (150) and the second landing pad (152) ; a first lower electrode (174) disposed on the first landing pad (150) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (172) disposed on the second landing pad (152) and extending in the direction substantially perpendicular to the substrate (100) (see col.5 lines 15- 60 wherein the first metal portions 150 include the metal layer 140 filling up the openings 122 and the second metal portion 152 include the metal layer 140 formed in the openings 122 and the landing pad 154 formed on the insulating layer 120, the first metal portions 150 and the second metal portions 152 include the same material but different heights and widths: a width of a top surface of the first metal portion 150 is smaller than a width of a top surface of the second metal portion 152, and a height H.sub.1 of the first metal portion 150 is smaller than a height H.sub.2 of the second metal portion 152) ; a dielectric layer extending along the first lower electrode (174) and the second lower electrode (172) ; and an upper electrode disposed on the dielectric layer (126) , wherein the first landing pad and the second landing pad protrude above an upper surface of the insulating pattern (120) with respect to a lower surface of the substrate, and the dielectric layer extends along portions of side surfaces of the first landing pad and the second landing pad that protrude above the upper surface of the insulating pattern (col.5 lines 60-67 wherein an insulating layer 126 and a plurality of crown-like structures are formed on the substrate 100 in the memory region 102 ; see col.4 lines 40-67 wherein t he insulating layer 120 includes an insulating material such as silicon oxide ( SiO ), but not limited to this ) . With respect to claim 13 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein the dielectric layer (126) extends along the upper surface of the insulating pattern (120) . Claims 1-3, 8-9, 12-16, 18-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wu et al. (US 2022/0238637 A1 hereinafter referred to as “Wu”) . With respect to claim 1 , Wu discloses, in Figs.1-9, a semiconductor device comprising: a substrate (10) comprising an active area (see Par.[0033] wherein a capacitor structure is formed through sequentially forming the lower electrode plate 20, the dielectric layer 30, the upper electrode plate and the protective layer 60 on the substrate 10 ) ; a first landing pad (11) connected to the active area and disposed on the substrate (10) ; a second landing pad (12) connected to the active area, and spaced apart from the first landing pad (11) , wherein the second landing pad (12) is disposed on the substrate; a first lower electrode (20) disposed on the first landing pad (11) and extending in a direction substantially perpendicular to the substrate (10) ; a second lower electrode (40) disposed on the second landing pad (12) and extending in the direction substantially perpendicular to the substrate (10) (see Par.[0035]-[0037] wherein the lower electrode plate 20 directly contacts with the contact pad 11; the upper electrode plate, the upper side of the contact portion 12 in the peripheral area may also be covered with the upper electrode plate (including an upper electrode 40 and an upper electrode filling layer 50), as shown in FIG. 2; it is necessary to cut off an excess material covering the contact portion 12 in the peripheral area to expose the contact portion 12 in the peripheral area, so as to facilitate the plug 91 to be connected with the contact portion 12 when the plug 91 is subsequently formed) ; a dielectric layer (30) extending along the first lower electrode (20) and the second lower electrode (40) ; and an upper electrode (50) disposed on the dielectric layer (30) , wherein a first upper surface of the first landing pad (11) is disposed below a second upper surface of the second landing pad (12) with respect to a lower surface of the substrate (see Par.[0037] wherein the lower electrode plate 20 is covered with the dielectric layer 30; at this time, the dielectric layer 30 may cover the contact portion 12 in the peripheral area ; a fter the surface of the dielectric layer 30 is covered with the upper electrode plate, the upper side of the contact portion 12 in the peripheral area may also be covered with the upper electrode plate (including an upper electrode 40 and an upper electrode filling layer 50), as shown in FIG. 2) . With respect to claim 2 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein a first lower surface of the first lower electrode (20) is disposed below a second lower surface of the second lower electrode ( 4 0) with respect to the lower surface of the substrate (10) (see Fig.9, wherein electrode 40 is disposed on electrode 20 over contact pad 11) . With respect to claim 3 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein the first lower electrode (20) has a first width at a first point and has a second width, which is greater than the first width, at a second point, wherein the second point is disposed above the first point with respect to the lower surface of the substrate (10) (see Fig.9, wherein lower portion of electrode 20 is smaller than that of upper portion of electrode 20 in region directly over substrate) . With respect to claim 8 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein a first material included in each of the first landing pad (11) and the second landing pad (12) is different from a second material included in each of the first lower electrode (20) and the second lower electrode (40) (see Par.[0106] wherein the material of the contact pad s 11 -12 includes, but is not limited to, tungsten ; see Par.[0112]-[0113] wherein the material of the lower electrode plate 20 includes, but is not limited to, titanium nitride ; the material of the upper electrode 40 includes, but is not limited to, titanium nitride ) . With respect to claim 9 , Wu discloses, in Figs.1-9, t he semiconductor device, further comprising an electrode support (70) disposed on a sidewall of the first lower electrode (20) and a sidewall of the second lower electrode (40) and supporting the first lower electrode (20) and the second lower electrode (40) (see Par.[0107]-[0109] wherein the first support layer 70 and the second support layer 80 may be made of the same material ; s pecifically, the first support layer 70 and the second support layer 80 may both include silicon nitride ) . With respect to claim 12 , Wu discloses, in Figs.1-9, a semiconductor device comprising: a substrate (10) comprising an active area (see Par.[0033] wherein a capacitor structure is formed through sequentially forming the lower electrode plate 20, the dielectric layer 30, the upper electrode plate and the protective layer 60 on the substrate 10); a first landing pad (11) connected to the active area and disposed on the substrate (10) ; a second landing pad (12) connected to the active area, and spaced apart from the first landing pad (11) , wherein the second landing pad (12) is disposed on the substrate (10) ; an insulating pattern /( insulating portion of substrate 10) disposed between the first landing pad (11) and the second landing pad (12) (see Par.[0045]-[0046] wherein the substrate 10 may include a silicon nitride layer, and the capacitor structure is directly arranged on the silicon nitride layer ; the substrate 10 may further include a portion formed by a silicon-containing material ; t he substrate 10 may be formed by any suitable materials, which includes, for example, at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium or carbon-doped silicon ) ; a first lower electrode (20) disposed on the first landing pad (11) and extending in a direction substantially perpendicular to the substrate (10) ; a second lower electrode (40) disposed on the second landing pad (12) and extending in the direction substantially perpendicular to the substrate (10) (see Par.[0035]-[0037] wherein the lower electrode plate 20 directly contacts with the contact pad 11; the upper electrode plate, the upper side of the contact portion 12 in the peripheral area may also be covered with the upper electrode plate (including an upper electrode 40 and an upper electrode filling layer 50), as shown in FIG. 2; it is necessary to cut off an excess material covering the contact portion 12 in the peripheral area to expose the contact portion 12 in the peripheral area, so as to facilitate the plug 91 to be connected with the contact portion 12 when the plug 91 is subsequently formed) ; a dielectric layer (30) extending along the first lower electrode (20) and the second lower electrode (40) ; and an upper electrode (50) disposed on the dielectric layer (30) , wherein the first landing pad (11) and the second landing pad (12) protrude above an upper surface of the insulating pattern /(insulating portion of substrate) with respect to a lower surface of the substrate (10) , and the dielectric layer (30) extends along portions of side surfaces of the first landing pad (11) and the second landing pad (12) that protrude above the upper surface of the insulating pattern /(insulating portion of substrate 10) (see Par.[0037] wherein the lower electrode plate 20 is covered with the dielectric layer 30; at this time, the dielectric layer 30 may cover the contact portion 12 in the peripheral area; after the surface of the dielectric layer 30 is covered with the upper electrode plate, the upper side of the contact portion 12 in the peripheral area may also be covered with the upper electrode plate (including an upper electrode 40 and an upper electrode filling layer 50), as shown in FIG. 2) . With respect to claim 13 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein the dielectric layer (30) extends along the upper surface of the insulating pattern /( SiN portion of substrate 10) (see Fig.9, wherein dielectric 30 over portion of substrate 10) . With respect to claim 14 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein a first lower surface of the first lower electrode (20) is disposed below a second lower surface of the second lower electrode (40) with respect to the lower surface of the substrate (10) (see Fig.9) . With respect to claim 15 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein the first lower electrode comprises: a first portion disposed below an upper surface of the second landing pad (12) ; and a second portion disposed above the upper surface of the second landing pad (12) and disposed on the first portion, wherein a width of the first portion is smaller than a portion of the second portion (see Fig.9, wherein lower portion of electrode 20 is smaller than that of upper portion of electrode 20 in region directly over substrate). With respect to claim 16 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein an upper surface of the second landing pad (12) is disposed above an upper surface of the first landing pad (11) with respect to the lower surface of the substrate (10) . With respect to claim 18 , Wu discloses, in Figs.1-9, t he semiconductor device, further comprising: a first liner (80) extending alongside surfaces of the first lower electrode (20) ; and a second liner (80) extending alongside surfaces of the second lower electrode (40) (see Par.[0107]-[0109] wherein the first support layer 70 and the second support layer 80 may be made of the same material; specifically, the first support layer 70 and the second support layer 80 may both include silicon nitride). With respect to claim 19 , Wu discloses, in Figs.1-9, t he semiconductor device, wherein each of the first lower electrode (20) and the second lower electrode (40) comprises titanium nitride ( SiN ), and each of the first landing pad (11) and the second landing pad (12) comprises tungsten (W) (see Par.[0106] wherein the material of the contact pads 11-12 includes, but is not limited to, tungsten; see Par.[0112]-[0113] wherein the material of the lower electrode plate 20 includes, but is not limited to, titanium nitride; the material of the upper electrode 40 includes, but is not limited to, titanium nitride). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-2, 4-5, 7-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 202 3 /0 112600 A1 hereinafter referred to as “ Yun ”) in view of Ho . With respect to claim 1 , Kim discloses, in Figs.1-15, a semiconductor device comprising: a substrate (10 0 ) comprising an active area (see Par.[00 39 ] wherein t he substrate 100 may be formed with unit elements necessary for forming a semiconductor element such as various types of active elements or passive elements ) ; a first landing pad (160) connected to the active area and disposed on the substrate (101) ; a second landing pad (160) connected to the active area, and spaced apart from the first landing pad, wherein the second landing pad (160) is disposed on the substrate (100) (see Par.[0086] wherein e ach of the lower portion 210BP_1 of the first lower electrode 210_1 and the lower portion 210BP_2 of the second lower electrode 210_2 may include a lower surface of the lower electrode 210 that comes into contact with (and is electrically connected to) a respective landing pad 160 ) ; a first lower electrode (210) disposed on the first landing pad (160) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (210) disposed on the second landing pad (160) and extending in the direction substantially perpendicular to the substrate (100) (see Par.[0035]-[0037] wherein a lower electrode 210, a capacitor insulating (e.g., dielectric) film 211, and an upper electrode 212 are not shown in FIG. 1 ) ; a dielectric layer ( 211 ) extending along the first lower electrode (210) and the second lower electrode (210) (see Par.[0 1 00 ] -[0102] wherein t he capacitor dielectric film 211 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof ) ; and an upper electrode (212) disposed on the dielectric layer ( 211 ). However, Kim does not explicitly disclose wherein a first upper surface of the first landing pad is disposed below a second upper surface of the second landing pad with respect to a lower surface of the substrate. Ho discloses, in Figs.1-6, a semiconductor device comprising: a substrate (100) comprising an active area (see col.3 lines 55-67, a plurality of shallow trench isolation (hereinafter abbreviated as STI) structures 106 are formed in the substrate 100 in the memory region 102 and the peripheral region 104); a first landing pad (140/152) connected to the active area and disposed on the substrate (100); a second landing pad (152) connected to the active area, and spaced apart from the first landing pad (140/150), wherein the second landing pad (152) is disposed on the substrate (100) (see col.5 lines 15-60 wherein the first metal portions 150 include the metal layer 140 filling up the openings 122 and the second metal portion 152 include the metal layer 140 formed in the openings 122 and the landing pad 154 formed on the insulating layer 120, the first metal portions 150 and the second metal portions 152 include the same material but different heights and widths: a width of a top surface of the first metal portion 150 is smaller than a width of a top surface of the second metal portion 152, and a height H.sub.1 of the first metal portion 150 is smaller than a height H.sub.2 of the second metal portion 152); a first lower electrode (174) disposed on the first landing pad (150) and extending in a direction substantially perpendicular to the substrate (100); a second lower electrode (172) disposed on the second landing pad (152) and extending in the direction substantially perpendicular to the substrate (100) (see col.6-7, the first connecting structures 160 are electrically connected to the storage nodes 174 and the second connecting structures 162 are electrically connected to the storage nodes 172); a dielectric layer (126) extending along the first lower electrode (174) and the second lower electrode (172) (see col.5 lines 60-67 wherein an insulating layer 126 and a plurality of crown-like structures are formed on the substrate 100 in the memory region 102); and an upper electrode/(upper electrical connections between the storage nodes 172, 174) disposed on the dielectric layer, wherein a first upper surface of the first landing pad (150) is disposed below a second upper surface of the second landing pad (152) with respect to a lower surface of the substrate (100) (see col7, lines 40-67 wherein the connecting structures including the landing pads, electrical connections between the storage nodes and the memory cells are constructed). Kim and Ho are analogous art because they are all directed to a semiconductor memory device , and one of ordinary skill in the art would have had a reasonable expectation of s uccess by modify ing Kim to include Ho because they are from the same field of endeavor. Therefore, i t would have been obvious to one of ordinary skill in the art at the time t he invention was made to modify the land pads heights in Kim by including land pads include different heights as t aught by Ho in order to utilize the process issue induced by different land pad pattern densities thereby the semiconductor device includes superior performance even when DRAM become more integrated and miniaturized . With respect to claim 2 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a first lower surface of the first lower electrode (174) is disposed below a second lower surface of the second lower electrode (172) with respect to the lower surface of the substrate. With respect to claim 4 , Kim discloses, in Figs.1-15 , t he semiconductor device, further comprising an insulating pattern (144) disposed between the first landing pad (160) and the second landing pad (160) , wherein an upper surface of the insulating pattern (144) is disposed below the upper surface of the first landing pad (160) with respect to the lower surface of the substrate (100) (Par.[0131] wherein the cell line capping film 144 may include, for example, at least one of a silicon nitride film, a silicon oxynitride, a silicon carbonitride, and a silicon oxycarbonitride ) . With respect to claim 5 , Kim discloses, in Figs.1-15, t he semiconductor device, wherein the dielectric layer (211) extends along the upper surface of the insulating pattern (144) . With respect to claim 7 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a lower surface of the upper electrode is disposed below the upper surface of the second landing pad with respect to the lower surface of the substrate. With respect to claim 8 , Kim discloses, in Figs.1-15, t he semiconductor device, wherein a first material included in each of the first landing pad (160) and the second landing pad (160) is different from a second material included in each of the first lower electrode (212) and the second lower electrode (212) (see Par.[0141] wherein t he landing pad 160 may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy ; see Par.[0113] wherein t he upper electrode 212 may include, for example, but is not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, or tantalum, etc.), or a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.) ) . With respect to claim 9 , Kim discloses, in Figs.1-15, t he semiconductor device, further comprising an electrode support (50, 60) disposed on a sidewall of the first lower electrode (212) and a sidewall of the second lower electrode (212) and supporting the first lower electrode (212) and the second lower electrode (212) (see Par.[ 0037] wherein a first electrode support 50, and a second electrode support 60 ) . With respect to claim 10 , Kim discloses, in Figs.1-15, t he semiconductor device, further comprising: a first liner /( portion of 211) extending alongside surfaces of the first lower electrode; and a second liner extending alongside surfaces of the second lower electrode. With respect to claim 11 , Kim discloses, in Figs.1-15, t he semiconductor device, wherein each of the first liner and the second liner comprises the material included in the second landing pad (160) (see Par.[0100]-[0102] wherein the capacitor dielectric film 211 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof ; see Par.[0052] wherein the lower electrode 210 may include, for example, but not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.); see Par.[0141] wherein the landing pad 160 may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy). With respect to claim 12 , Kim discloses, in Figs.1-15, a semiconductor device comprising: a substrate (100) comprising an active area (see Par.[0039] wherein the substrate 100 may be formed with unit elements necessary for forming a semiconductor element such as various types of active elements or passive elements) ; a first landing pad (160) connected to the active area and disposed on the substrate (100) ; a second landing pad (160) connected to the active area, and spaced apart from the first landing pad, wherein the second landing pad is disposed on the substrate (see Par.[0086] wherein each of the lower portion 210BP_1 of the first lower electrode 210_1 and the lower portion 210BP_2 of the second lower electrode 210_2 may include a lower surface of the lower electrode 210 that comes into contact with (and is electrically connected to) a respective landing pad 160) ; an insulating pattern disposed between the first landing pad and the second landing pad; a first lower electrode (210) disposed on the first landing pad and extending in a direction substantially perpendicular to the substrate (see Par.[0035]-[0037] wherein a lower electrode 210, a capacitor insulating (e.g., dielectric) film 211, and an upper electrode 212 are not shown in FIG. 1) ; a second lower electrode disposed on the second landing pad and extending in the direction substantially perpendicular to the substrate; a dielectric layer (211) extending along the first lower electrode (210) and the second lower electrode (210) (see Par.[0035]-[0037] wherein a lower electrode 210, a capacitor insulating (e.g., dielectric) film 211, and an upper electrode 212 are not shown in FIG. 1); a dielectric layer (165) extending along the first lower electrode (210) and the second lower electrode (210) (see Par.[0144] wherein the etching stop film 165 may include, for example, at least one of silicon nitride ( SiN ), silicon carbonitride ( SiCN ), silicon oxycarbonitride ( SiOCN ), silicon oxycarbide ( SiOC ), and silicon boronitride ( SiBN )) ; and an upper electrode (212) disposed on the dielectric layer (211) , wherein the first landing pad and the second landing pad protrude above an upper surface of the insulating pattern (144) with respect to a lower surface of the substrate, and the dielectric layer (211) extends along portions of side surfaces of the first landing pad and the second landing pad that protrude above the upper surface of the insulating pattern (144) . However, Kim does not explicitly disclose wherein a first upper surface of the first landing pad is disposed below a second upper surface of the second landing pad with respect to a lower surface of the substrate. Ho discloses, in Figs.1-6 , a semiconductor device comprising: a substrate (100) comprising an active area (see col.3 lines 55-67, a plurality of shallow trench isolation (hereinafter abbreviated as STI) structures 106 are formed in the substrate 100 in the memory region 102 and the peripheral region 104); a first landing pad (150) connected to the active area and disposed on the substrate (100); a second landing pad (152) connected to the active area, and spaced apart from the first landing pad (150), wherein the second landing pad (152) is disposed on the substrate (100); an insulating pattern disposed between the first landing pad (150) and the second landing pad (152); a first lower electrode (174) disposed on the first landing pad (150) and extending in a direction substantially perpendicular to the substrate (100); a second lower electrode (172) disposed on the second landing pad (152) and extending in the direction substantially perpendicular to the substrate (100) (see col.5 lines 15-60 wherein the first metal portions 150 include the metal layer 140 filling up the openings 122 and the second metal portion 152 include the metal layer 140 formed in the openings 122 and the landing pad 154 formed on the insulating layer 120, the first metal portions 150 and the second metal portions 152 include the same material but different heights and widths: a width of a top surface of the first metal portion 150 is smaller than a width of a top surface of the second metal portion 152, and a height H.sub.1 of the first metal portion 150 is smaller than a height H.sub.2 of the second metal portion 152); a dielectric layer extending along the first lower electrode (174) and the second lower electrode (172); and an upper electrode disposed on the dielectric layer (126), wherein the first landing pad and the second landing pad protrude above an upper surface of the insulating pattern (120) with respect to a lower surface of the substrate, and the dielectric layer extends along portions of side surfaces of the first landing pad and the second landing pad that protrude above the upper surface of the insulating pattern (col.5 lines 60-67 wherein an insulating layer 126 and a plurality of crown-like structures are formed on the substrate 100 in the memory region 102; see col.4 lines 40-67 wherein the insulating layer 120 includes an insulating material such as silicon oxide ( SiO ), but not limited to this). Kim and Ho are analogous art because they are all directed to a semiconductor memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Kim to include Ho because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the land pads heights in Kim by including land pads include different heights as taught by Ho in order to utilize the process issue induced by different land pad pattern densities thereby the semiconductor device includes superior performance even when DRAM become more integrated and miniaturized. With respect to claim 13 , Kim discloses, in Figs.1-15, t he semiconductor device, wherein the dielectric layer (211) extends along the upper surface of the insulating pattern (144) . With respect to claim 14 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a first lower surface of the first lower electrode is disposed below a second lower surface of the second lower electrode with respect to the lower surface of the substrate. With respect to claim 16 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein an upper surface of the second landing pad is disposed above an upper surface of the first landing pad with respect to the lower surface of the substrate. With respect to claim 17 , Ho discloses, in Figs.1-6, t he semiconductor device, wherein a lowermost surface of the dielectric layer is disposed below each of a lower surface of the first lower electrode and a lower surface of the second lower electrode with respect to the lower surface of the substrate. With respect to claim 18 , Kim discloses, in Figs.1-15, t he semiconductor device, further comprising: a first liner extending alongside surfaces of the first lower electrode; and a second liner extending alongside surfaces of the second lower electrode. With respect to claim 19 , Kim discloses, in Figs.1-15, t he semiconductor device, wherein each of the first lower electrode and the second lower electrode comprises titanium nitride ( SiN ), and each of the first landing pad and the second landing pad comprises tungsten (W) (see Par.[0052] wherein t he lower electrode 210 may include, for example, but not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.) ; see Par.[0141] wherein t he landing pad 160 may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy ) . With respect to claim 20 , Kim discloses, in Figs.1-15, a semiconductor device comprising: a gate trench (115) disposed in a substrate (100) ; a gate electrode (112) filling a portion of the gate trench (115) (see Par.[0119]-[0120] wherein t he cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive film 114 that are formed inside the substrate 100 and the cell element separation film 105 ) ; a storage contact (120) disposed on at least one side of the gate electrode (112) and connected to the substrate (100) (see Par.[0132] wherein the cell insulating film 130 may be formed on a portion of the substrate 100 and the cell element separation film 105 on which the bit line contact 146 and the storage contact 120 are not formed ) ; a first landing pad (160) disposed on the storage contact (120) ; a second landing pad (160) disposed on the storage contact (120) and spaced apart from the first land pad (160) (see Par.[0140]-[0142] wherein t he landing pad 160 may be formed on the storage contact 120. The landing pad 160 may be electrically connected to the storage contact 120 ) ; a first lower electrode (210) disposed on the first landing pad (160) and extending in a direction substantially perpendicular to the substrate (100) ; a second lower electrode (210) disposed on the second landing pad (160) and extending in the direction substantially perpendicular to the substrate (100) (see Par.[0145]-[0146] wherein t he lower electrode 210 may include a first sub-lower electrode and a second sub-lower electrode that are spaced apart from each other ) ; an insulating pattern (144) disposed between the first landing pad (160) and the second landing pad (160) (see Par.[0131] wherein the cell line capping film 144 may include, for example, at least one of a silicon nitride film, a silicon oxynitride, a silicon carbonitride, and a silicon oxycarbonitride ) ; an electrode support (50) spaced apart from the insulating pattern (144) , and disposed on a sidewall of the first lower electrode (210) and a sidewall of the second lower electrode (210) , wherein the electrode support supports the first lower electrode and the second lower electrode (see Par.[0053]-[0055] wherein t he first electrode support 50 may come into contact with the side walls of the lower electrode 210 ) ; a dielectric layer (211) extending along the first lower electrode (210) , the second lower electrode (210) , the insulating pattern (144) and the electrode support (50) (see Par.[0100] wherein t he capacitor dielectric film 211 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and