DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 – 12, 14, and 16 – 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 7, 10 – 12, 14, and 16 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 5,977,626) in view of Rinne (US 2007/0182004).
Regarding claim 1, Wang teaches (FIG. 3, 7):
A method of comprising:
affixinq a plurality of conductive connectors (26a) of a first type;
after the forming and affixing, affixing a die pad of a leadframe (32) on a backside of the semiconductor die, the leadframe including a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die toward a plane of the RDL substrate (FIG. 3); and
encapsulating with an encapsulant (30) the semiconductor die and the leadframe, a lead tip portion of each lead exposed through the encapsulant, wherein a conductive connector of the first type is not affixed to the lead tip portion of each lead (FIG. 3, adhesive material 34).
Wang teaches BGA mounting using solder balls, but fails to expressly disclose a redistribution layer (RDL) substrate over an active side of a semiconductor die, the RDL substrate having a plurality of under-bump metallization (UBM) structures.
However, it is entirely conventional to include chip scale integrated RDL and UBM structures for enabling BGA mounting of semiconductor devices as evidenced by Rinne, with the further advantage of improving connection robustness by including compliant dielectric layers in the RDL.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a conventional RDL and UBM structure as evidenced by Rinne in the BGA mounted device of Wang for the predictable advantage of improving connection quality.
Regarding claim 2, Wang teaches (FIG. 7C):
The method of claim 1, wherein the plurality of leads of the leadframe are pre- bent such that the plurality of leads substantially surround the sidewalls of the semiconductor die after affixing the die pad on the backside of the semiconductor die.
Regarding claim 3, Wang teaches (FIG. 7C):
The method of claim 1, wherein a lead tip portion of each lead the plurality of leads are substantially coplanar with the UBM structures of the RDL substrate.
Regarding claim 4, Wang teaches (FIG. 3):
The method of claim 1, wherein the plurality of leads and the die pad of the leadframe are formed from a same contiguous metal.
Regarding claim 5, Wang teaches (solder balls 26a):
The method of claim 1, wherein the conductive connectors of the first type are characterized as conductive ball connectors.
Regarding claim 6, Wang teaches (FIG. 3, adhesive 34):
The method of claim 1, wherein the lead tip regions of the plurality of leads are configured for connection to a printed circuit board.
Regarding claim 7, Wang teaches:
The method of claim 1, wherein the leadframe is configured as electromagnetic interference (EMI) shield (col 4, line 9 – 30).
Regarding claim 10, Wang teaches (FIG. 3):
A semiconductor device comprising:
a semiconductor die (22) having a plurality of bond pads located at an active side of the semiconductor die;
a plurality of conductive ball connectors (26a);
a die pad of a leadframe (32) affixed on a backside of the semiconductor die, the leadframe including a plurality of leads connected to the die pad and bent such that the leads extend vertically from the die pad toward a plane of the RDL substrate (FIG. 3); and
an encapsulant (30) encapsulating the semiconductor die and at least a portion of the leadframe, a lead tip portion of each lead of the plurality of leads exposed through the encapsulant, wherein the lead tip portion of each lead of the plurality of leads does not have a conductive ball connector affixed to it (FIG. 3).
Wang teaches BGA mounting using solder balls, but fails to expressly disclose a redistribution layer (RDL) substrate over an active side of a semiconductor die, the RDL substrate having a plurality of under-bump metallization (UBM) structures configured for attachment of ball connectors.
However, it is entirely conventional to include chip scale integrated RDL and UBM structures for enabling BGA mounting of semiconductor devices as evidenced by Rinne, with the further advantage of improving connection robustness by including compliant dielectric layers in the RDL.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a conventional RDL and UBM structure as evidenced by Rinne in the BGA mounted device of Wang for the predictable advantage of improving connection quality.
Regarding claim 11, Wang teaches:
The semiconductor device of claim 10, wherein the lead tip portion of each lead of the plurality of leads is substantially coplanar with the plurality of UBM structures (FIG. 3).
Regarding claim 12, Wang teaches:
The semiconductor device of claim 10, wherein the plurality of leads of the leadframe are bent and extend vertically such that the plurality of leads substantially surround the sidewalls of the semiconductor die (FIG. 3).
Regarding claim 14, Wang teaches:
The semiconductor device of claim 10, wherein a backside of the die pad of the leadframe is exposed through a top surface of the encapsulant (FIG. 3).
Regarding claim 16, Wang teaches (FIG. 3, 7):
A method of comprising:
affixing a plurality of conductive ball connectors (26a);
after the forming and the affixing, affixing a die pad of a leadframe (32) on a backside of the semiconductor die (22), the leadframe including a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die to a lead tip portion (FIG. 3); and
encapsulating with an encapsulant (30) the semiconductor die and the leadframe, the lead tip portion of each lead exposed through the encapsulant (FIG. 3).
Wang teaches BGA mounting using solder balls, but fails to expressly disclose a redistribution layer (RDL) substrate over an active side of a semiconductor die, the RDL substrate having a plurality of under-bump metallization (UBM) structures.
However, it is entirely conventional to include chip scale integrated RDL and UBM structures for enabling BGA mounting of semiconductor devices as evidenced by Rinne, with the further advantage of improving connection robustness by including compliant dielectric layers in the RDL.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a conventional RDL and UBM structure as evidenced by Rinne in the BGA mounted device of Wang for the predictable advantage of improving connection quality.
Regarding claim 17, Wang teaches:
The method of claim 16, wherein the lead tip portion of each lead exposed through the encapsulant is substantially coplanar with the plurality of UBM structures of the RDL substrate (FIG. 3).
Regarding claim 18, Wang teaches (FIG. 7c):
The method of claim 16, wherein the plurality of leads of the leadframe are pre-bent such that the plurality of leads are distributed around the sidewalls of the semiconductor die after affixing the die pad on the backside of the semiconductor die.
Regarding claim 19, Wang teaches:
The method of claim 16, further comprising exposing a backside of the die pad of the leadframe through the encapsulant (FIG. 3).
Regarding claim 20, Wang teaches (FIG. 7c):
The method of claim 16, wherein the plurality of leads and the die pad of the leadframe are formed from a same contiguous metal.
Regarding claim 21, Wang teaches (FIG. 3):
The method of claim 1 further comprising affixing the plurality of conductive connectors of a first type and the lead tip portions of each lead to conductive structures of a circuit board (20).
Regarding claim 22, Wang teaches:
The method of claim 16 further comprising affixing the plurality of conductive ball connectors and the lead tip portions of each lead to conductive structures of a circuit board (20).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 5,977,626) in view of Rinne (US 2007/0182004) as applied to claim 1 above, and further in view of Otremba et al. (US 2015/0214133).
Regarding claim 8, Wang teaches exposed die pad for heat spreader purposes, but fails to expressly disclose:
The method of claim 1, further comprising grinding a top surface of the encapsulant to expose a backside of the die pad of the leadframe.
However, Otremba teaches grinding back encapsulant to expose a metal pad for connecting a heat sink.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a grinding process as disclosed by Otremba in the method of Wang to expose a plane of the metallic leadframe structure for improved mounting performance of a heat sink structure.
Regarding claim 9, Otremba teaches:
The method of claim 8, further comprising attaching a heat sink or heat spreader to the exposed die pad of the leadframe (60).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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