DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claims 11-20 are withdrawn.
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to the product claims 1-10, in the reply filed on 02/12/2026 is acknowledged.
Claims 11-20, Group II, withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/12/2026.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/30/2024 and 02/18/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US PGPub 2019/0206874; herein known as Wang) in view of Juengling et al. (US PGPub 2020/0185396; herein known as Juengling).
Regarding claim 1, Wang teaches (Fig. 10) a memory device comprising: a memory array region (R1, [0022]); an insulating layer (31, [0021]) disposed in the memory array region; a digit line (BL, [0021]) contacting the dielectric, the digit line having a metal composition ([0021]); a transistor (see figure, [0022]) in a periphery (R2, [0022]) to the memory array region (R1, [0020]); and a metal contact (82, [0030]) contacting a metal gate (43B, [0022]) of the transistor.
Wang does not explicitly teach wherein the insulating layer is a dielectric.
Juengling teaches (Fig. 23) a dielectric (16, [0044]).
Because Wang and Juengling are both directed toward memory devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Juengling and of Wang to include a dielectric, as use of a dielectric as an appropriate insulating layer is known in the art, as taught by Juengling ([0044]).
Regarding claim 3, Wang in view of Juengling teaches (Wang, Fig. 10) the memory device of claim 1, wherein the metal composition includes tungsten (Wang, [0030]).
Regarding claim 4, Wang in view of Juengling teaches (Wang, Fig. 10) the memory device of claim 1, wherein the at most one metallic region (42A, [0023]) includes tungsten silicide ([0023]) extending above and from a top level of the dielectric ([0023], 41 may optionally not be deposited), and the at most one metal barrier region (42B, [0023]) includes tungsten silicide ([0023]).
Regarding claim 6, Wang in view of Juengling teaches (Wang, Fig. 10) the memory device of claim 1 wherein the digit line is a tungsten digit line ([0030]) wherein the digit line (BL, 43A, [0023]) is directly on and extending above the dielectric (31, layers 41A and 42A may not be deposited, [0023]) and wherein the metal contact is directly on the metal gate ([0031]).
Regarding claim 9, Wang in view of Juengling teaches the memory device of claim 1, but does not explicitly teach wherein the transistor is a transistor of a complementary metal oxide semiconductor (CMOS) device.
Wang teaches a transistor for control of transmission through bit lines of the device ([0020]), as is known in the art.
Juengling teaches wherein periphery circuitry for control of bit lines of a device can be achieved using a CMOS device ([0066]), as is known in the art.
Because Wang and Juengling both teach periphery transistor structures for control of a device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the CMOS device of Jeungling for the MOS of Wang for the predictable result of controlling the bit lines of the device. See MPEP 2143.I.B.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Juengling as applied to claim 1 above, and further in view of Fumagalli et al. (US PGPub 2021/0043579; herein known as Fumagalli).
Regarding claim 2, Wang in view of Juengling teaches the memory device of claim 1, but does not explicitly teach wherein the memory device has digit line contacts in the dielectric for the digit line, the digit line contacts arranged in a pattern for a memory array of the memory array region.
Wang in view of Juengling teaches connection of the digit lines to source/drain regions through contacts (Juengling, [0065]).
Fugamalli teaches wherein the memory device (10, [0033]) has digit line contacts (38, [0033]) in the dielectric (40, [0033]) the digit line contacts arranged in a pattern for a memory array of the memory array region ([0033]) for the purpose of providing connection from the digit line to the source/drain region ([0033]).
Because Wang in view of Juengling and Fugamalli are both directed toward memory devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine prior art elements of Wang in view of Juengling and Fugamalli to include wherein the memory device has digit line contacts in the dielectric for the digit line, the digit line contacts arranged in a pattern for a memory array of the memory array region according to the known method of Fugamalli, to yield the predictable result of connecting digit lines to source/drain regions. See MPEP 2143.I.A.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Juengling as applied to claim 1 above, and further in view of Chen et al. (US PGPub 2022/0122992; herein known as Chen).
Regarding claim 5, Wang in view of Juengling teaches the memory device of claim 4, wherein the tungsten silicide extends above the top level of the dielectric, but does not explicitly teach by about 3 nm and the tungsten silicide extends above a top level of the metal gate by about 3 nm.
Chen teaches wherein a silicide layer may be formed having a thickness between 2 nm and 20 nm ([0080]).
Because Wang in view of Juengling and Chen are directed toward barrier layers of memory devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang in view of Juengling and of Chen to include wherein the tungsten silicide extends above the top level of the dielectric by about 3 nm and the tungsten silicide extends above a top level of the metal gate by about 3 nm in order to provide reduction of contact resistance (Chen, [0080]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Juengling as applied to claim 6 above, and further in view of Goswami et al. (US PGPub 2008/0273410; herein known as Goswami).
Regarding claim 7, Wang in view of Juengling teach the memory device of claim 6, but do not explicitly teach wherein the tungsten digit line and the metal contact have a thickness of about 14 nm.
Goswami teaches wherein a tungsten digit line is preferably less than 500 angstroms thick (50 nanometers), as thickness of a tungsten conductor is a result effective variable, for the result of affecting the capacitance of a memory device, which improves write and read performance, as well as improving failure rates ([0028, 0007]), while lower bounds of the thickness are dictated by degradation of performance characteristics ([0028]).
Absent a teaching of criticality or of unexpected results of digit line thickness or metal contact thickness of 14nm of the claimed invention, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang in view of Juengling and of Goswami to include wherein the tungsten digit line and the metal contact have a thickness of about 14nm, as a result effective variable. See MPEP 2144.05(II)(B).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Juengling as applied to claim 1 above, and further in view of Youn et al. (KR 20110025472; herein known as Youn, translation provided for reference).
Regarding claim 8, Wang in view of Juengling teaches the memory device of claim 1, but does not explicitly teach wherein a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 9 nm.
Youn teaches wherein a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is a result effective variable, modifying the aspect ratio of the metal contact in the peripheral circuit area, which improves the process margin of the contact (Page 5, Lines 10-14). Because Wang in view of Juengling and Youn are directed toward memory devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang in view of Juengling and of Youn to include wherein a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 9 nm as a result effective variable that may be optimized by a person of ordinary skill in the art, absent a teaching of criticality of 9nm, in the claimed invention. See MPEP 2144.05(II)(B).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Juengling as applied to claim 1 above, and further in view of Chen et al. (US PGPub 2019/0027487; herein known as Chen).
Regarding claim 10, Wang in view of Juengling teaches the memory device of claim 1, but does not explicitly teach wherein the metal gate of the transistor is a high-k metal gate.
Chen teaches wherein the metal gate of the transistor is a high-k metal gate ([0039])
Because Wang in view of Juengling and Chen are directed toward memory devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang in view of Juengling and of Chen to include wherein the metal gate of the transistor is a high-k metal gate in order to allow for a narrower/shorter channel length and therefore improve performance of the memory device and reduce a size of a die or chip on which the memory device is fabricated (Chen, [0040]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812