DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6, and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20160027795, of record) in view of Adetutu et al. (US 2006/0017110).
Regarding claim 1, Jung et al. discloses, as shown in Figures 1, 4A-4D and 13-14, a memory device comprising:
a memory array region (CAR,CTR, [0022]) having a dielectric (130) disposed in the memory array region;
a digit line (BL,BPLG,CL,WCT,WPLG,[0034]-[0038]) on the dielectric in the memory array region, the digit line having a metal composition (e.g., tungsten [0111]);
a transistor (MOS transistor, 30, [0064]-[0065]) in a periphery (PERI, [0054]) to the memory array region, the transistor having a gate stack including a metal gate (23, [0067], gate pattern may include at least one of metal and metal silicide, etc.);
a metal contact (ICL,PCT,PPLG, e.g., tungsten [0111]) on the gate stack of the transistor and coupled to the transistor (30) (Figure 13), the metal contact having the metal composition of the digit line (e.g., tungsten [0111]).
Jung et al. discloses the gate pattern (23) may include at least one a metal silicide and metal, etc. ([0067)]. Jung et al. does not disclose the gate pattern comprising the metal silicide above and contacting the metal gate of the transistor. However, Adetutu et al. discloses a gate pattern comprising a metal silicide (32,48,50,68,90) above and contacting a metal gate (15,18) of the transistor (11,13,51,53, etc.) Note [0020] and Figures 1-11 of Adetutu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the gate pattern of Jung et al. comprising the metal silicide above and contacting the metal gate of the transistor, such as taught by Adetutu et al. in order to further reduce the contact resistance between the metal contact and the metal gate.
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Regarding claim 2, Jung et al. and Adetutu et al. disclose the metal silicide has a thickness.
Note that the term “defined by a thickness of polysilicon completely convertible to the metal silicide in fabrication” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 6, Jung et al. and Adetutu et al. disclose the metal composition includes tungsten ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)).
Regarding claim 8, Jung et al. and Adetutu et al. disclose the memory device includes the metal silicide on and contacting the metal gate ([0067], gate pattern may include at least one of metal and metal silicide) and the metal contact (PPLG, e.g., tungsten [0111]) on and contacting the metal silicide.
Regarding claim 9, Jung et al. and Adetutu et al. disclose the digit line (BL,BPLG,CL,WCT,
WPLG, [0034]-[0038]) is on and contacting the dielectric (130).
Regarding claim 10, Jung et al. and Adetutu et al. disclose the claimed invention including the memory device as explained in the above rejection. Jung et al. and Adetutu et al. further disclose, as shown in [0055], that the height of the peripheral logic structure is smaller than the height of the cell array structure. Jung et al. and Adetutu et al. do not disclose a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 14 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, height, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, height, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 11, Jung et al. and Adetutu et al. disclose the transistor is a transistor of a complementary metal oxide semiconductor (CMOS) device ([0064], the CMOS device comprises the PMOS transistor and the NMOS transistor), with the metal gate being a high-k metal gate (0111]).
Claim(s) 3-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20160027795, of record) in view of Adetutu et al. (US 2006/0017110) and further in view of Liou et al. (PN 5,162,884, of record).
Regarding claim 3, Jung et al. and Adetutu et al. disclose the claimed invention including the memory device as explained in the above rejection. Jung et al. and Adetutu et al. do not disclose the metal silicide is titanium silicide. However, Liou et al. discloses a metal silicide is tungsten silicide or titanium silicide. Note Figures 1 and 15, Col. 8, line 63 – Col. 9, line10, Col. 13, line 64 – Col. 14, line 9 of Liou et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the metal silicide of Jung et al. and Adetutu et al. being titanium silicide, such as taught by Liou et al. since tungsten silicide is easier to form and it has higher conductivity.
Regarding claim 4, Jung et al., Adetutu et al. and Liuo et al. disclose the memory device has a metal barrier region between the titanium silicide and the metal contact, the metal barrier region on and contacting the metal silicide, with the metal contact on and contacting the metal barrier region ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)).
Regarding claims 5 and 7, Jung et al., Adetutu et al. and Liuo et al. disclose the digit line separate from the dielectric by the metal barrier region ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)). Jung et al., Adetutu et al. and Liuo et al. do not disclose the metal barrier region includes tungsten silicide. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the metal barrier region of Jung et al., Adetutu et al. and Liuo et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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