Prosecution Insights
Last updated: April 19, 2026
Application No. 18/236,556

METAL SILICIDE IN INTEGRATION OF MEMORY ARRAY WITH PERIPHERY

Non-Final OA §102§103
Filed
Aug 22, 2023
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
861 granted / 984 resolved
+19.5% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
30 currently pending
Career history
1014
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
42.0%
+2.0% vs TC avg
§102
40.1%
+0.1% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 984 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention of Group I, Claims 1-11, in the reply filed on 12/16/2025 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/16/2025. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 6, 8-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 20160027795). Regarding claim 1, Jung et al. discloses, as shown in Figures 1, 4A-4D and 13-14, a memory device comprising: a memory array region (CAR,CTR, [0022]) having a dielectric (130) disposed in the memory array region; a digit line (BL,BPLG,CL,WCT,WPLG,[0034]-[0038]) on the dielectric in the memory array region, the digit line having a metal composition; a transistor (MOS transistor, 30, [0064]-[0065]) in a periphery (PERI, [0054]) to the memory array region; a metal contact (ICL,PCT,PPLG, e.g., tungsten [0111]) coupled to the transistor (30) (Figure 13), the metal contact having the metal composition of the digit line (e.g., tungsten [0111]); and a metal silicide (23) above and contacting a metal gate (23) of the transistor ([0067], gate pattern may include at least one of metal and metal silicide), the metal silicide coupled to the metal contact. Regarding claim 2, Jung et al. discloses the metal silicide has a thickness. Note that the term “defined by a thickness of polysilicon completely convertible to the metal silicide in fabrication” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Regarding claim 6, Jung et al. discloses the metal composition includes tungsten ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)). Regarding claim 8, Jung et al. discloses the memory device includes the metal silicide on and contacting the metal gate ([0067], gate pattern may include at least one of metal and metal silicide) and the metal contact (PPLG, e.g., tungsten [0111]) on and contacting the metal silicide. Regarding claim 9, Jung et al. discloses the digit line (BL,BPLG,CL,WCT,WPLG,[0034]-[0038]) is on and contacting the dielectric (130). Regarding claim 11, Jung et al. discloses the transistor is a transistor of a complementary metal oxide semiconductor (CMOS) device ([0064], the CMOS device comprises the PMOS transistor and the NMOS transistor), with the metal gate being a high-k metal gate (0111]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20160027795) in view of Liou et al. (PN 5,162,884). Regarding claim 3, Jung et al. discloses the claimed invention including the memory device as explained in the above rejection. Jung et al. does not disclose the metal silicide is titanium silicide. However, Liou et al. discloses a metal silicide is tungsten silicide or titanium silicide. Note Figures 1 and 15, Col. 8, line 63 – Col. 9, line10, Col. 13, line 64 – Col. 14, line 9 of Liou et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the metal silicide of Jung et al. being titanium silicide, such as taught by Liou et al. since tungsten silicide is easier to form and it has higher conductivity. Regarding claim 4, Jung et al. and Liuo et al. disclose the memory device has a metal barrier region between the titanium silicide and the metal contact, the metal barrier region on and contacting the metal silicide, with the metal contact on and contacting the metal barrier region ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)). Regarding claims 5 and 7, Jung et al. and Liuo et al. disclose the digit line separate from the dielectric by the metal barrier region ([0111], WPLG and PPLG may include sequentially forming a barrier metal layer (e.g., a metal nitride layer) and a metal layer (e.g., a tungsten layer)). Jung et al. and Liuo et al. do not disclose the metal barrier region includes tungsten silicide. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the metal barrier region of Jung et al. and Liuo et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20160027795). Jung et al. discloses the claimed invention including the memory device as explained in the above rejection. Jung et al. further discloses, as shown in [0055], that the height of the peripheral logic structure is smaller than the height of the cell array structure. Jung et al. does not disclose a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 14 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, height, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, height, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Jan 09, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 984 resolved cases by this examiner. Grant probability derived from career allow rate.

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