Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II, claims 1-3, 5-13, 15-20 in the reply filed on 02/25/2026 is acknowledged. The traversal is on the ground(s) that search and examination of the entire application can be made without serious burden and are not mutually exclusive. This is not found persuasive because as shown in application figures even though some of the elements are common/usuable together but other elements and processing parameters are distinct and the species require a different field of search (e.g., searching different subclasses or electronic resources or non patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Claims 4, 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/25/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10-13, 15, 18-20 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 2021/0398890 A1) in view of Hong et al (USPGPUB 2015/0179547 A1).
Regarding claim 1: Kim teaches in Fig. 1 about a semiconductor package, comprising:
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a first structure 1000 that includes a conductive pattern 110/210 etc.;
a second structure 2000 spaced apart from the first structure;
a pillar structure 930 between the first structure and the second structure, the pillar structure electrically connecting the first structure to the second structure (as shown); and
a semiconductor chip 700 between the first structure and the second structure, wherein the pillar structure includes an inner pillar on the conductive pattern and an outer pillar that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
Kim does not explicitly show wherein the pillar structure includes an inner pillar on the conductive pattern and an outer pillar that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
Hong teaches in Fig. 2e about wherein the pillar structure includes an inner pillar 215a on the conductive pattern 218 and an outer pillar 213a that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
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Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Hong’s hybrid pillar (213a+215a) structure to modify Kim’s pillar structure device to avoid additional defects in the layers of a metallization system (not shown) subsequently formed above the TSV's and the contact structure layer, such as voids, gaps, and additional depressions and/or dished regions, thereby potentially leading to decreased product yield and reduced product performance (Hong, [0020] and to avoid reduced product quality and performance due to thermally induced stresses (Hong, [0022]).
Regarding claim 2: Hong teaches as marked above wherein the top surface of the inner pillar is parallel to a first direction, and the sidewall of the inner pillar is parallel to a second direction that intersects the first direction.
Regarding claim 3: Hong teaches in Fig. 2e above wherein a width in the first direction of the top surface of the inner pillar 215a s less than a length in the second direction of the sidewall of the inner pillar.
Regarding claim 8: Kim and Hong teach wherein the outer pillar is spaced apart from the conductive pattern (considering 118b or 118c as the conductive pattern in Hon’s device).
Regarding claims 10-11: As explained above, claims 1-3, Kim in view of Hong teaches all the limitations.
Regarding claim 12: Hong teaches in Fig. 2e wherein the outer pillar includes: an upper portion at a level higher than a level of a top surface of the inner pillar; and a lower portion at a level lower than the level of the top surface of the inner pillar.
Regarding claim 13: Hong teaches in Fig. 2e wherein the lower portion of the outer pillar has a cylindrical shape that surrounds the inner pillar, and the upper portion of the outer pillar has a pillar shape.
Regarding claim 15: Kim and Hong teaches wherein a bottom surface of the lower portion of the outer pillar is spaced apart from a top surface of the conductive pattern (considering 118b or 118c as the conductive pattern in Hon’s device).
Regarding claim 18: Kim teaches in Fig. 1, [0029] wherein the conductive pattern includes a conductive layer 110, a metal layer on the conductive layer 210, and a seed layer 310 on the metal layer, the seed layer includes a conductive material the same as a conductive material of the inner pillar and the outer pillar, and the metal layer includes a conductive material different from the conductive material of the seed layer, the inner pillar, and the outer pillar.
Regarding claim 19: As explained in claim 1, Kim in view of Hong teaches all the limitations. Kim further teaches in Fig. 1 about a second semiconductor chip 800 mounted on the second structure 2000; and a molding layer 950 between the first structure and the second structure, the molding layer surrounding the first semiconductor chip 700 and the pillar structure 930.
Regarding claim 20: Hong does not explicitly talk about wherein a width in the second direction of the inner pillar is equal to or less than about 0.5 times a width in the second direction of the outer pillar.
However Hong shows in Fig. 2e wherein a width in the second direction of the inner pillar is equal to or less than about 0.5 times a width in the second direction of the outer pillar.
Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28 F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.
Claims 1, 5 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 2021/0398890 A1) in view of Choi et al (US PGPUB 2013/0161824 A1).
Regarding claim 1: Kim teaches in Fig. 1 about a semiconductor package, comprising:
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a first structure 1000 that includes a conductive pattern 110/210/310 etc.;
a second structure 2000 spaced apart from the first structure;
a pillar structure 930 between the first structure and the second structure, the pillar structure electrically connecting the first structure to the second structure (as shown); and
a semiconductor chip 700 between the first structure and the second structure, wherein the pillar structure includes an inner pillar on the conductive pattern and an outer pillar that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
Kim does not explicitly show wherein the pillar structure includes an inner pillar on the conductive pattern and an outer pillar that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
Choi teaches in Fig. 4-5 about wherein the pillar structure includes an inner pillar 138 on the conductive pattern 142 and an outer pillar (comprises 136+152) that surrounds the inner pillar, wherein the outer pillar is in contact with a sidewall and a top surface of the inner pillar.
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Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Choi’s pillar structure to modify Kim’s pillar structure device to avoid stress particular at the junction between the conductive TSV and base material of the semiconductor wafer. The stress can cause cracking, degraded electrical performance, and other defects in the semiconductor wafer (Choi, [0008])
Regarding claim 5: Choi teaches wherein the outer pillar and the inner pillar include the same conductive material ([0044] teaches 136 comprising copper, [0044] teaches 138 comprising copper, [0052] teaches 152 comprising copper).
Claims 6-7 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 2021/0398890 A1) in view of Choi et al (US PGPUB 2013/0161824 A1) and further in view of Lee et al. (US PGPUB 2022/0068869 A1)
Regarding claim 6: Kim in view of Choi does not explicitly talk about wherein an average size of grains of the inner pillar is less than an average size of grains of the outer pillar.
Lee teaches in [0015] - [0016], [0028] and Fig. 1E, 4 about having different copper crystal grain sizes depending on parameters like temperature, current density etc. of electroplating process formation of the via/tsv to have the plated conductive layer with a desired thickness and quality.
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Lee’s method of pillar formation to modify Kim’s pillar structure device to have the feature as claimed to have a desired thickness and quality with different crystal grain sizes (Lee, [0028]).
Regarding claim 7: Kim in view of Choi does not explicitly talk about wherein a density of grain boundaries in the inner pillar and a density of grain boundaries in the outer pillar are less than a density of grain boundaries at an interface between the inner pillar and the outer pillar.
Lee teaches in [0015] - [0016], [0028] and Fig. 1E, 4 about having different copper crystal grain sizes depending on parameters like temperature, current density etc. of electroplating process formation of the via/tsv to have the plated conductive layer with a desired thickness and quality.
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to use Lee’s method of pillar formation to modify Kim’s pillar structure device to have the feature as claimed to have a desired thickness and quality with different crystal grain sizes (Lee, [0028]).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is” a molding layer that surrounds the pillar structure, wherein the molding layer includes an intervening part between the outer pillar and the conductive pattern” in combination with other limitations as a whole
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “a molding layer that surrounds the semiconductor chip and the pillar structure, wherein the molding layer includes an intervening part between the bottom surface of the lower portion of the outer pillar and the top surface of the conductive pattern”.
Claim 17 is also allowable being dependent on allowable claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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