DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0105335 A1 (Fitzgerald) further in view of US 2013/0284885 A1 (Chen).
Re claims 1, 2 and 8, Fitzgerald teaches method for fabricating an image sensor array (semiconductor structure 800), the method comprising:
forming, on a semiconductor donor wafer comprising silicon (monocrystalline silicon layer 141/131 [0065-0067]), one or more recesses;
growing, on the one or more recesses, an absorption layer comprising germanium (second monocrystalline semiconductor layer 220/222 [0068]);
forming back-end processing such as forming interconnects and CMOS (step 360 [0070]) (Figs. 8 and 9).
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However, Fitzgerald does not explicitly teach any of the details of the back end processing such as:
forming a first interconnect layer on the absorption layer, the first interconnect layer comprising a plurality of interconnects configured to be coupled to the absorption layer;
forming, on a semiconductor carrier wafer, integrated circuitry for controlling the image sensor array;
forming the integrated circuitry, forming a second interconnect layer on the semiconductor carrier wafer, the second interconnect layer comprising a plurality of interconnects coupled to the integrated circuitry; and
bonding the first interconnect layer with the second interconnect layer (claim 1);
after bonding the first interconnect layer with the second interconnect layer, removing a portion of the semiconductor donor wafer (claim 2);
forming lens elements over the image sensor array, wherein each of the lens elements is arranged to guide light to a respective photodiode of the image sensor array, and forming wavelength filters over the image sensor array, wherein each of the wavelength filters is configured to filter light for a respective photodiode of the image sensor array (claim 8).
Chen teaches forming a CMOS photodetector (sensor device Fig. 1a) having silicon and/or germanium photodiodes (photodiodes 102 [0014-0015]) formed in a first silicon substrate (substrate 101) and transistor circuitry (transistors 103) in the sensor portion (sensor chip 100/101) and wherein a first interconnect layer (IMD layer 104) is formed over the first silicon substrate, a second interconnect layer (IMD layer 204) is formed on a second silicon substrate (substrate 201 [0023]), and bonding the first interconnect layer of the first silicon substrate with the second interconnect layer of the second silicon substrate, such that the circuitry is in between the photodiodes region and the second silicon substrate and forming a filter layer (color filter 108) and a lens layer (microlens 109) over the photodiodes 102 and removing a portion of the first silicon substrate to form vias (TSV 105) after bonding (Fig. 1a [0013-0023]).
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It would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the back-end processing for CMOS photodetectors as taught by Chen in the method of making a photodetector of Fitzgerald.
The motivation to do so is that Fitzgerald does not elaborate at all about appropriate back end processing of the photodetectors after the initial germanium and silicon photo regions are formed. Therefore the ordinary skilled artisan would look to Chen to ascertain how the control and readout circuitry is formed in the back end processes mentioned in Fitzgerald.
Re claim 4, Fitzgerald further teaches wherein growing, on the one or more recesses, the absorption layer comprises: growing the germanium on the one or more recesses by a selective epitaxial growth, such that the germanium is at least partially embedded in the one or more recesses ([0067-0068]).
Re claim 5, Fitzgerald further teaches wherein growing, on the one or more recesses, the germanium further comprises: polishing the absorption layer to planarize the germanium to be fully embedded in the one or more recesses ([0064] the resulting epitaxial fill in the recess is coplanar with the surrounding silicon layer 141 after a blanket deposition and epitaxial growth of 220/222 Fig. 8).
Re claim 6, Fitzgerald further teaches after forming the one or more recesses, forming, within the one or more recesses, one or more sidewall spacers (spacer 230).
Re claim 7, Fitzgerald further teaches wherein forming the one or more sidewall spacers comprises: depositing, on the semiconductor donor wafer, a dielectric layer; and performing a directional etch of the dielectric layer ([0068] the insulating layer is blanket deposited over the patterned structure and then etched, the fact that the resulting spacer structure is only on the sidewalls of the recess implies the etch was anisotropic not isotropic).
Re claim 9, Fitzgerald further teaches wherein each of the one or more recesses corresponds to a pixel in the image sensor array ([0121]).
Re claim 10, Fitzgerald further teaches wherein a shape of each of the one or more recesses comprises a square or a circle (in the top view of the photodetector of Fitzgerald in Fig. 20 , photodetector 2063 is square shaped).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0105335 A1 (Fitzgerald) further in view of US 2013/0284885 A1 (Chen) further in view of US 2015/0171146 A1 (Ooki).
Re claim 3, Fitzgerald and Chen teach the method of claim 1, however, Chen does not explicitly teach wherein removing the portion of the semiconductor donor wafer comprises polishing the semiconductor donor wafer.
Ooki teaches forming a photodetector wherein after bonding the sensor and control chips together the top surface of the photodiode substrate is polished before forming the color filters and microlens array (Fig. 17 [0272]).
It would have been obvious to one of ordinary skill in the art at the time of filing the invention to perform a polishing of the exposed photodiode substrate of Chen after bonding the ASIC and before the forming the filter and lens array as taught by Ooki.
The motivation to do so is that the polishing process provides the predictable result of planarizing the top surface of the photodiode substrate layer to obtain a flat surface before subsequent deposition of additional layers and optical arrangements thereon (Fig. 17).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896