Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the newly amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210233859 A1) in view of Kuo et al. (US 20220223512 A1)
CLAIM 1. Lee et al. discloses a semiconductor package comprising:
a redistribution layer 500 (Lee et al. ¶29 & Fig. 1A);
a three-dimensional integrated circuit (3D IC) structure 300 on the redistribution layer 500 (Lee et al. ¶39 & Fig. 1A – Note: 3D IC is defined in written description as a chip/die integrated circuit);
a plurality of conductive posts 200 on the redistribution layer adjacent to the 3D IC structure (Lee et al. ¶29 & Fig. 1A);
a molding material 400 [¶29] on the redistribution layer and encapsulating the 3D IC structure and the plurality of conductive posts 200 (Lee et al. ¶108 & Fig. 1A); and
a printed circuit board (PCB) 100 on the molding material 400 (Lee et al. ¶29-30 & Fig. 1A).
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Lee et al. may be silent upon the capability of integrating first and second semiconductor chip die into the package structure, however at the time of the invention the inclusion of multiple stacked chip die was a known capable option to a PHOSITA.
Kuo teaches and analogous package structure to that of Lee and as claimed, Kou discloses a package comprising:
a redistribution layer 302 (Kuo et al. & Fig. 7);
a three-dimensional integrated circuit (3D IC) structure 306+312 on the redistribution layer 302, the 3D IC structure comprising a first semiconductor chip die 312 and a second semiconductor chip die 306 below the first chip die (Kuo et al. Fig. 7 – Note: 3D IC is defined in written description as a chip/die integrated circuit);
a plurality of conductive posts 318 on the redistribution layer adjacent to the 3D IC structure (Kuo Fig. 7);
a molding material 322 on the redistribution layer 302 and encapsulating the 3D IC structure and the plurality of conductive posts (Kuo Fig. 7); and
a printed circuit board (PCB) 324 (Kuo teaches a RDL 324, however this structure is a functional and structural alternative to a PCB) on the molding material 322 (Kuo Fig. 7);
wherein the second semiconductor chip die 312 comprises a plurality of second bonding pads (While not clearly labeled, Kuo discloses the semiconductor package structure 700 includes a first semiconductor die 312 and second semiconductor die 306 stacked vertically over the frontside RDL 302. The second semiconductor 306contains a plurality of through vias 308. These vies extend from the top surface to the bottom surface of die 306 to provide electrical pathways. These through vias 308 are “electrically coupled to the frontside redistribution layer 302”. Consequently for the top die 312 to be electrically coupled to th multi-capacitor structure through the through via 308 and the redistribution layer 302,” a conductive connection must exist where the top of the via 308 meets the bottom of the die 312.
While the term “bond pad” is not explicitly labeled in the diagram for this specific junction, Kuo identifies that components stacked in this manner use conductive structures for interconnection. In similar vertically stacked embodiments withing the document conductive structures such as microbumps [¶45] are dispose between a die and its supporting substrate or another die to facilitate these electrical couplings. Because die 312 is “disposed over the bottom semiconductor die 306” and must access the capacitor 310 via through vias 308, conductive pads are the interface are at least oblivious if not inherent physical mechanism required to bridge the electrical gap between the two chips.)
and a second insulating layer on an upper surface of the second semiconductor chip die facing the lower surface of the first semiconductor chip die (Kuo Fig. 7 - Non labeled layer located between chips 312 and 306. The layer is required to be a insulating layer, at least to prevent shorting between vias 308.).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the semiconductor chips of Lee with vertically stacked plurality of chips as taught by Kou, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Alternatively, It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the top RDL level of Kuo with a PCB as taught by Lee, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 2. Lee et al. in view of Kuo teach a semiconductor package of claim 1, wherein a coefficient of thermal expansion of the redistribution layer 500 is greater than a coefficient of thermal expansion of the PCB 100 (Lee et al. ¶56 & Fig. 1A)1.
CLAIM 3. Lee et al. in view of Kuo teach a a semiconductor package of claim 1, wherein a modulus of elasticity of the redistribution layer 500 is smaller than a modulus of elasticity of the PCB 100 (Lee et al. ¶57 & Fig. 1A)2.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Kuo in view of Ecton (US 20230197679 A1).
CLAIM 4. Lee et al. in view of Kuo teach a a semiconductor package of claim 1, wherein the redistribution layer comprises: a polymer dielectric [which would be capable of being a PID material, see below.]; and a plurality of first conductive lines in the polymer dielectric (Lee et al. ¶37).
Lee et al., while disclosing specific polymer dielectrics such as PBO, BCB, and polyimide, may be silent on whether these materials are photo-imageable Lee et al., while disclosing specific polymer dielectrics such as PBO, BCB, and polyimide, may be silent on whether these materials are photo-imageable (Lee et al. ¶37). However, selecting a photosensitive formulation for these materials would have been an obvious expectation and choice for one of ordinary skill in the art (POSITA) at the time of the invention. These materials are commonly formulated to be photosensitive and used as Photo-Imageable Dielectrics (PID).
Furthermore, PID materials were well-known and conventionally used in the art for redistribution layers (RDL) in semiconductor packages at the time the invention was made. Ecton et al. provides explicit teaching that corroborates this conventional use within an analogous semiconductor package structure. Ecton discloses the specific combination of materials preferred by the Applicant, resulting in the claimed relative coefficient of thermal expansion (CTE) relationship. Specifically, Ecton teaches the use of an FR-4 printed circuit board (PCB) (See ¶[0030] & Fig. 1)3 and a PID RDL (See ¶[0039] & Fig. 1)4.
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It would have been obvious to one having ordinary skill in the art at the time the invention was made to select PID for an RDL dielectric, as "it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art" (In re Leshin, 125 USPQ 416).
Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Kuo in view of Marimuthu et al. (US 20190088603 A1).
CLAIM 5. Lee et al. in view of Kuo teach a a semiconductor package of claim 1, however may be silent upon wherein the PCB comprises: a dielectric comprising glass fibers and epoxy; and a plurality of second conductive lines in the dielectric. The use of reinforcement features within PCB substrates for added strength was a known and conventional practice. (See Marimuthu et al., paragraph [0044]).
Marimuthu et al. discloses an analogous semiconductor package structure involving a mold-encapsulated die on a PCB board with an RDL on the opposing side, similar to the claimed invention and other cited references. Marimuthu et al. specifically teaches:
PCB units 170 begin with a core substrate 172. Core substrate 172 includes one or more laminated layers of polytetrafluoroethylene pre-impregnated (prepreg), FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, and other reinforcement fibers or fabrics. In one embodiment, core substrate 172 is a composite with woven fiber and filler. In another embodiment, core substrate 172 is formed from an encapsulant or molding compound. Alternatively, core substrate 172 includes one or more insulating or passivation layers.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the standard PCB of the prior art with the reinforced PCB structure taught by Marimuthu et al. Applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
CLAIM 6. Lee et al. in view of Kuo in view of Marimuthu et al. discloses a semiconductor package of claim 1, wherein the molding material comprises an epoxy molding compound (EMC) (Lee et al. ¶62)5.
CLAIM 7. Lee et al. in view of Kuo in view of Marimuthu et al. discloses a et al. in view of Ecton et al. in view of Marimuthu et al. discloses a semiconductor package of claim 1, wherein a die attach film (DAF) is between the 3D IC structure and the PCB (Lee et al. ¶61)6.
Claim(s) 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Kuo in view of See Marimuthu et al. in view of Uzoh et al. (US 20150380377 A1).
CLAIM 8. Lee et al. in view of Kuo discloses a semiconductor package comprising: a redistribution layer 500; a three-dimensional integrated circuit (3D IC) structure 300 on the redistribution layer 500, the 3D IC structure comprising a first semiconductor chip die 300 and a second semiconductor chip die below the first semiconductor chip die (Note: Lee et al. may only disclose a single die; however, the concept of a three-dimensional integrated circuit (3D IC) utilizing a plurality of stacked chips or dies was well known in the prior art.
For instance, Uzoh et al., in Figure 6B, discloses an analogous semiconductor package that incorporates multiple stacked chips/dies [626/627/629], PCB 301, RDL 628, and posts. It would have been an obvious modification for one of ordinary skill in the art (POSITA) to adapt the structure of Lee et al. to incorporate first, second, or additional stacked dies. Such a modification would be a simple matter of design choice for the predictable purposes of scaling the device, increasing complexity, or achieving known advantages of vertical integration. (See MPEP 2144.04 regarding routine optimization and design choices See below regarding Kuo further demonstrating first and second die stacked withing an analogous package.).
a plurality of conductive posts 200 on the redistribution layer 500 adjacent to the 3D IC structure 300; a molding material 400 on the redistribution layer 500 and encapsulating the 3D IC structure and the plurality of conductive posts; a printed circuit board (PCB) 100 on the molding material 400; and a third semiconductor chip die 200 on the PCB 100, wherein a lower surface of each conductive post of the plurality of conductive posts is on the redistribution layer and an upper surface of each conductive post of the plurality of conductive posts is below the PCB (i.e. posts are sandwiched between RDL level and PCB level), and wherein a die attach film (DAF) 320 is between an upper surface of the first semiconductor chip die and the PCB 100 and conductive connection members 310 are between a lower surface of the second semiconductor chip die and the redistribution layer 500 (Lee et al. Fig. 1D as modified by Uzoh et al. Figs. 6B).
Kuo teaches and analogous package structure to that of Lee and as claimed, Kou discloses a package comprising:
a redistribution layer 302 (Kuo et al. & Fig. 7);
a three-dimensional integrated circuit (3D IC) structure 306+312 on the redistribution layer 302, the 3D IC structure comprising a first semiconductor chip die 312 and a second semiconductor chip die 306 below the first chip die (Kuo et al. Fig. 7 – Note: 3D IC is defined in written description as a chip/die integrated circuit);
a plurality of conductive posts 318 on the redistribution layer adjacent to the 3D IC structure (Kuo Fig. 7);
a molding material 322 on the redistribution layer 302 and encapsulating the 3D IC structure and the plurality of conductive posts (Kuo Fig. 7); and
a printed circuit board (PCB) 324 (Kuo teaches a RDL 324, however this structure is a functional and structural alternative to a PCB) on the molding material 322 (Kuo Fig. 7);
a third semiconductor chip die 330 on the PCB/RDL (Kuo fig. 7);
wherein a lower surface of each conductive post 318 of the plurality of conductive posts is on the redistribution layer and an upper surface of each conductive post of the plurality of conductive posts is below the PCB/RDL 324 (Kuo Fig. 7), and
wherein a die attach film (DAF) is between an upper surface of the first semiconductor chip die and the PCB (A standard depiction of a DAF is observable in in Fig. 7, however not labeled or described in the written description. Note, Lee teaches layers as such are known to be DAF layers. (Lee et al. ¶61)) and conductive connection members are between a lower surface of the second semiconductor chip die and the redistribution layer, wherein the first semiconductor chip die comprises a plurality of first bonding pads and a first insulating layer on a lower surface of the first semiconductor chip die, and wherein the second semiconductor chip die 312 comprises a plurality of second bonding pads (While not clearly labeled, Kuo discloses the semiconductor package structure 700 includes a first semiconductor die 312 and second semiconductor die 306 stacked vertically over the frontside RDL 302. The second semiconductor 306contains a plurality of through vias 308. These vies extend from the top surface to the bottom surface of die 306 to provide electrical pathways. These through vias 308 are “electrically coupled to the frontside redistribution layer 302”. Consequently for the top die 312 to be electrically coupled to th multi-capacitor structure through the through via 308 and the redistribution layer 302,” a conductive connection must exist where the top of the via 308 meets the bottom of the die 312.
While the term “bond pad” is not explicitly labeled in the diagram for this specific junction, Kuo identifies that components stacked in this manner use conductive structures for interconnection. In similar vertically stacked embodiments withing the document conductive structures such as microbumps [¶45] are dispose between a die and its supporting substrate or another die to facilitate these electrical couplings. Because die 312 is “disposed over the bottom semiconductor die 306” and must access the capacitor 310 via through vias 308, conductive pads are the interface are at least oblivious if not inherent physical mechanism required to bridge the electrical gap between the two chips.)
and a second insulating layer on an upper surface of the second semiconductor chip die facing the lower surface of the first semiconductor chip die (Kuo Fig. 7 - Non labeled layer located between chips 312 and 306. The layer is required to be a insulating layer, at least to prevent shorting between vias 308.).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the semiconductor chips of Lee with vertically stacked plurality of chips as taught by Kou, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Alternatively, It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the top RDL level of Kuo with a PCB as taught by Lee, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 11. Lee et al. in view of Kuo in view of Uzoh et al. discloses a semiconductor package of claim 10, wherein each first bonding pad of the plurality of first bonding pads is directly on each second bonding pad of the plurality of second bonding pads (Lee et al. Fig. 1D as modified by Uzoh et al. Fig. 6B– Uzoh et al. demonstrates the die/chips each include insulating layers and bond pads when stacked. See Fig. 6E-5 and ¶62 teaching capability of Bumps/pads 623 connecting die/chips).
CLAIM 12. Lee et al. in view of Kuo in view of Uzoh et al. discloses a semiconductor package of claim 8, wherein he plurality of first bonding pads and the plurality of second bonding pads comprise copper (Cu) (Uzoh et and ¶35-36, 44 – Cu is a conventional metal for bond pads and micro bumps.).
CLAIM 13. Lee et al. in view of Kuo in view of Uzoh et al. discloses a semiconductor package of claim 8, wherein the first insulating layer is directly on the second insulating layer (Lee et al. Fig. 1D as modified by Uzoh et al. Fig. 6B- stacking of die/chips results in the insulating layers of the die/chips to be also be on each other respectively.).
CLAIM 14. Lee et al.. in view of Kuo in view of Uzoh et al. discloses a semiconductor package of claim 8, wherein the first insulating layer and the second insulating layer comprise silicon oxide (Lee et al. ¶37 – Silicon oxide is disclosed as a conventional insulating material used for providing insulation over a chip or die. The simple selection of silicon oxide for this purpose would have been an obvious design choice for one of ordinary skill in the art at the time of the invention.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/24/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Lee et al. -- [0056] “In the semiconductor package 10 according to some embodiments of the disclosure, materials of the front-side redistribution layer 500 and the back-side wiring substrate 100 may differ from each other. The front-side redistribution layer 500 may include at least one of a polymer, nitride, etc. used in an RDL formation process. The back-side wiring substrate 100 may be a PCB substrate and, as such, may include epoxy or FR-4. Accordingly, the coefficient of thermal expansion (CTE) of the front-side redistribution layer 500 may be higher than that of the back-side wiring substrate 100. The CTE of the back-side wiring substrate 100 may be 1 ppm/° C. to 20 ppm/° C. The CTE of the front-side redistribution layer 500 may be 45 ppm/° C. to 80 ppm/° C.”
2 Lee et al. -- [0057] In addition, the modulus of elasticity of the back-side wiring substrate 100 may be higher than that of the front-side redistribution layer 500. The modulus of elasticity of the back-side wiring substrate 100 may be 20 GPa to 40 GPa. The modulus of elasticity of the front-side redistribution layer 500 may be less than 10 GPa.
3 Ecton et al. – [0030] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard printed circuit board (PCB) processes,…
4 Ecton et al. -- [0039] ….In some embodiments, the conductive vias 194 in the second RDL 148-2 may be formed using a lithographic process (e.g., by patterning vias, laminating a dielectric, and planarizing), a photo-imageable dielectric (PID) process (e.g., by laminating a PID, exposing the PID to form via openings, and providing a conductive material in the openings to form the conductive vias), or a laser drilling process (e.g., by forming via openings in a dielectric material and providing a conductive material in the openings to form the conductive vias).
5 Lee et al. -- [0062] Referring to FIG. 4C, the method may include providing an encapsulator 400 on the first surface of the back-side wiring substrate 100, thereby covering or overlapping on side surfaces and/or upper surfaces of the connectors 200 and the semiconductor chip 300. The encapsulator 400 may be formed through a molding process or a lamination process for a molding sheet. The encapsulator 400 may be formed to have a sufficient thickness preventing the connectors 200 and the chip bumps 320 from being externally exposed. The encapsulator 400 may include thermosetting resin such as epoxy resin, thermoplastic resin such as polyimide, resin composed of the thermosetting or thermoplastic resin and a reinforcement included therein, or the like. In addition, the encapsulator 400 may include a molding material such as an epoxy molding compound (EMC) or a photosensitive material such as a photo-imageable encapsulant (PIE).
6 Lee et al. – “[0061] Referring to FIG. 4B, the method may include mounting the semiconductor chip 300 in the chip mounting area MA on the first surface of the back-side wiring substrate 100, and bonding the semiconductor chip 300. The semiconductor chip 300 may be bonded to the back-side wiring substrate 100 by a chip adhesive film 320 such as a die attach film (DAF)… “