DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 08/22/2023 has been considered.
Drawings
The drawings filed on 08/22/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 08/22/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 9 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Fujino (US 2021/0043458).
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Regarding clam 1, Fujino (US 2021/0043458) discloses:
A semiconductor device, comprising:
a semiconductor layer including a first semiconductor region (n-type source layer 15) of a first conductivity type, a second semiconductor region (p-type base layer 13, ¶0017) contacting the first semiconductor region, the second semiconductor region being of a second conductivity type, and a third semiconductor region (n-type drift layer 11, ¶0017) located so that a portion of the second semiconductor region (13) is positioned between the first semiconductor region (15) and the third semiconductor region (11), the third semiconductor region (11) being of the first conductivity type;
a first electrode (30, ¶0018) electrically connected with the first semiconductor region (15);
a second electrode (20, ¶0015) electrically connected with the third semiconductor region (11);
a control electrode (40, ¶0015) facing the first (15), second (13), and third semiconductor regions (11) via an insulating film (43, ¶0016); and
a connection region (50, ¶0023) positioned between the first electrode (30) and the first semiconductor region (15), the connection region electrically connecting the first electrode (30) and the first semiconductor region (15),
the connection region including a compound of a first metallic element and Si (57, ¶0023, ¶0040), the first metallic element being at least a compound of Pt and Si (¶0030),
the connection region including a first part (53, ¶0030) adjacent to an n-type region (n-type layer 15) of the semiconductor layer in a first direction (y-direction), a peak position of a concentration distribution of the first metallic element (Pt) in the first direction (y-direction) of the first part (53) being between the n-type region (15) and a peak position of a concentration distribution of Pt in the first direction of the first part (53, ¶0044 discloses the Pt in silicide region 57 is thermally diffused downward, in the y-direction).
Regarding claim 2, Fujino further discloses:
wherein the first conductivity type is an n-type, the second conductivity type is a p-type, and the first part (53) is between the first semiconductor region (15) and the first electrode (30).
Regarding claim 3, Fujino further discloses:
wherein the connection region includes:
a first region (53) including the compound of the first metallic element and Si, at least a portion of the first region being positioned between the first semiconductor region and the first electrode and being in contact with the first semiconductor region; and
a second region (57) including the compound of Pt and Si, at least a portion of the second region being positioned between the first region and the first electrode and being in contact with the first electrode.
Regarding claim 4, Fujino further discloses:
a fourth semiconductor region, of the second conductivity type (p-type layer 17, ¶0017), the second semiconductor region (13) contacting the fourth semiconductor region (17), and having a lower second-conductivity- type impurity concentration than the fourth semiconductor region ¶0021) , the connection region (50) being positioned between the first electrode (30) and the fourth semiconductor region (17), the connection region electrically connecting the first electrode (30) and the fourth semiconductor region (17).
Regarding claim 5, Fujino further discloses:
a fourth semiconductor region of the second conductivity type (p-type region 17), the second semiconductor region (13) contacting the fourth semiconductor region, and having a lower second-conductivity- type impurity concentration than the fourth semiconductor region (¶0021), the connection region (50) being positioned between the first electrode (30) and the fourth semiconductor region (17), the connection region (50) electrically connecting the first electrode (30) and the fourth semiconductor region (17), the fourth semiconductor region (17) contacting the second region (13).
Regarding claim 9, Fujino discloses:
A semiconductor device, comprising:
a semiconductor layer including a first semiconductor region (15) of a first conductivity type, a second semiconductor region (13) contacting the first semiconductor region, the second semiconductor region being of a second conductivity type, and a third semiconductor region (11) located so that a portion of the second semiconductor region (13) is positioned between the first semiconductor region (15) and the third semiconductor region (11), the third semiconductor region (11) being of the first conductivity type;
a first electrode (30) electrically connected with the first semiconductor region (15); a second electrode (20, ¶0015) electrically connected with the third semiconductor region (11);
a control electrode (40) facing the first (15), second (13), and third (11) semiconductor regions via an insulating film (43); and
a connection region (50) positioned between the first electrode (20) and the first semiconductor region (15), the connection region electrically connecting the first electrode (20) and the first semiconductor region (15), the connection region including a compound of a first metallic element and Si (¶0030), the first metallic element being a compound of Pt and Si, the connection region (50) including a first region (53) contacting an n-type region (15) of the semiconductor layer, the first region including the first metallic element (¶0030), and a second region (57) contacting the first electrode (20), the second region including Pt (¶0030), the second region not including the first metallic element or having a lower first metallic element concentration than the first region (¶0021.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art does not disclose “the second semiconductor region contacting the fourth semiconductor region, and having a lower second-conductivity- type impurity concentration than the fourth semiconductor region, the connection region being positioned between the first electrode and the fourth semiconductor region, the connection region electrically connecting the first electrode and the fourth semiconductor region, the first conductivity type being a p-type, the second conductivity type being an n-type, the first part being between the fourth semiconductor region and the first electrode” in combination with the remaining claimed features.
Claims 10 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art does not disclose “implanting a first metallic element into at least a portion of a surface layer region of the semiconductor layer, the surface layer region including a portion of the first semiconductor region, the first metallic element being at least one selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W; depositing Pt on the surface layer region, or implanting Pt into a region of the surface layer region higher than a position into which at least a portion of the first metallic element is implanted; forming a first electrode on a connection region, the connection region being formed by reacting the semiconductor layer and the first metallic element and reacting the semiconductor layer and Pt in the surface layer region, the first electrode being electrically connected with the first semiconductor region; and forming a second electrode electrically connected with the third semiconductor region” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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