DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14, 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naitoh, US 2006/0060949.
Regarding claim 14, Naitoh discloses; a film package comprising: a film substrate having a first side surface and a second side surface opposing each other in a first direction (attached Fig. 3 below and [0079]; substrate 32 has first side surface and second side surface opposing each other in first direction), each of the first side surface and the second side surface extending in a second direction perpendicular to the first direction (attached Fig.3 below); at least one semiconductor chip disposed on the film substrate and extending lengthwise in the first direction (attached Fig.3 below) ; input terminals arranged on the film substrate along the first side surface in the second direction (attached Fig.3 below) , output terminals arranged on the film substrate along the second side surface (attached Fig.3 below) , and wirings formed on the film substrate and electrically connecting the input terminals and the output terminals to the at least one semiconductor chip (Fig.1-3, 6 and [0079-0082]; Cu wires 12 connecting the input terminals 23 and the output terminals 22 to the chip 33,34 ); and a protective layer covering the wirings on the film substrate (Fig. 1-3, 6 and [0053, 0079]; Cu wires 12 are covered with a polyimide solder resist 14).
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Regarding claim 16, Naitoh discloses; in a plan view, the input terminals and the output terminals do not overlap with the protective layer (Fig. 1-3, 6; input terminals 23 and output terminals 22 exposed by solder resist 14).
Regarding claim 19, Naitoh discloses; a film package comprising: a film substrate having a first side surface and a second side surface opposing each other in a first direction and extending in a second direction perpendicular to the first direction (attached Fig. 3 below and [0079]; substrate 32 has first side surface and second side surface opposing each other in first direction and extending in a second direction); at least one semiconductor chip disposed on the film substrate and having first edges opposing each other in the first direction (attached Fig. 3 below) and second edges opposing each other in the second direction (attached Fig. 3 below); input terminals arranged on the film substrate along the second direction to be adjacent to the first side surface (attached Fig. 3 below); output terminals arranged on the film substrate along the second direction to be adjacent to the second side surface (attached Fig. 3 below); and wirings on the film substrate, each wiring extending from one of the second edges of the at least semiconductor chip to one terminal of the input terminals and the output terminals (Fig.1-3, 6 and [0079-0082]; Cu wires 12 connecting the input terminals 23 and the output terminals 22 to the chip 33,34); wherein a length of each of the second edges in the first direction is greater than a length of each of the first edges in the second direction (attached Fig. 3 below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Naitoh, US 2006/0060949, as applied to claims 14, 16 and 19 above and further in view of Jung- US 2022/0246530.
Regarding claim 15, Naitoh substantially discloses the invention including a semiconductor device on a scaled-down flexible substrate has side surfaces opposing each other in the first direction, extending in the second direction but silent about a length of the film substrate in the second direction is in a range from about 180 mm to about 220 mm, and a length of the film substrate in the first direction is in a range from about 30 mm to about 70 mm. However, Jung shows that a length 210L in X-direction is greater than the length 210S in Y-direction and a short axis length 210S of the bridge film 210, about 35 mm to about 156 mm (Fig. 4 and [0075]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Naitoh by providing a length of the film substrate in the second direction is in a range from about 180 mm to about 220 mm, and a length of the film substrate in the first direction is in a range from about 30 mm to about 70 mm, to provides a chip-on-film (COF) package capable of improving a dead space of a display panel, and a display apparatus including the COF package ([0004]).
Claims 17 and 18 rejected under 35 U.S.C. 103 as being unpatentable over Naitoh, US 2006/0060949, as applied to claims 14, 16 and 19 above and further in view of Min, US 2020/0211972.
Regarding claims 17 and 18, Naitoh discloses in claim 17; the wirings include a front wiring extending on a front surface of the film substrate on which the at least one semiconductor chip is disposed (Fig.1-3, 6 and [0079-0082]; Cu wires 12 connecting the input terminals 23 and the output terminals 22 to the chips 33, 34 on top surface of substrate 11). Naitoh discloses in claim 18; in a plan view, the front wiring extends from one or more sides, extending in the first direction, of the at least one semiconductor chip the input terminals and the output terminals (attached Fig. 3 above and Fig.1-3, 6 and [0079-0082]; Cu wires 12 connecting the input terminals 23 and the output terminals 22 to the chips 33,34 on top surface of substrate 11, extending in the first direction). Naitoh substantially discloses the invention including a semiconductor device on a scaled-down flexible substrate with Cu wires connecting the input terminals and the output terminals to the chips on top surface of substrate, extending in the first direction has side surfaces opposing each other in the first direction but silent about a rear wiring extending on a rear surface opposite to the front surface in claim 17 and the rear wiring extends from one or more sides, extending in the first direction, of the at least one semiconductor chip to at least one of the input terminals and the output terminals in claim 18. However, Min teaches that a rear wiring extending on a rear surface opposite to the front surface (Fig.8 and [0084-0085]; wiring layout view illustrating a second surface 110b of a film substrate 110) and the rear wiring extends from one or more sides, extending in the first direction, of the at least one semiconductor chip to at least one of the input terminals and the output terminals (Fig.8 and [0084-0085]; first wire 150 and second wire 250 extend along the second surface 110b between the first and second semiconductor chip 310, 320 and second bonding region BR2). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Naitoh by providing a rear wiring extending on a rear surface opposite to the front surface in claim 17 and the rear wiring extends from one or more sides, extending in the first direction, of the at least one semiconductor chip to at least one of the input terminals and the output terminals in claim 18, so that to provides the display device a second bonding region extends along the second surface of the substrate and include an output wire connecting the output pad and the second bonding region and extending at least partially along the second surface of the film substrate [0009].
Claim(s) 1and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Min, US 2020/0211972, in view of Naitoh, US 2006/0060949.
Regarding claim 1, Min discloses; a film package comprising: a film substrate having a front surface and a rear surface opposing each other (Fig. 2-8 and [0046]; film substrate 110 include first and second surfaces 110a and 110b, which are opposite to each other), a first side surface and a second side surface opposing each other in a first direction (attached Fig. 7 below and Fig.2-8; film substrate 110 has opposite side surfaces, opposing each other in Y-direction), and a third side surface and a fourth side surface opposing each other in a second direction, intersecting the first direction (Fig.2-8; film substrate 110 has opposite side surfaces, opposing each other in X-direction ); a first semiconductor chip and a second semiconductor chip disposed on the front surface of the film substrate (Fig.2-8 and [0045]; the first and second semiconductor chips 310 and 320 disposed on surface 110a) and spaced apart in the second direction (Fig.2-8 and [0045]; the first and second semiconductor chips 310 and 320 disposed on surface 110a, spaced apart in the X-direction); a front protective layer (Fig.2-8 and [0068]; resist film 120 cover the wires on the film substrate 110) extending lengthwise in the second direction to cover at least a portion of the front surface of the film substrate and having openings in which the first and second semiconductor chips are disposed (Fig.2-8 and [0068]; the resist film 120 may expose the first chip pads 315 and the second chip pads 325); a rear protective layer (Fig.2-8 and [0068]; resist film 120 cover the wires on the film substrate 110 on surface 110b) extending lengthwise in the second direction to cover at least a portion of the rear surface of the film substrate; and a plurality of wiring patterns including, a front wiring (Fig.2-8 and [0084-0085]; wiring layout view illustrating a first surface 110a of a film substrate 110) positioned between the front protective layer and the front surface of the film substrate, electrically connected (Fig.2-8 and [0088,0104]; the fourth wire 250, a fifth wire 240, and a sixth wire 260 connect the first semiconductor chip 310 and the first wire 150, a second wire 140, a third wire 160 connect the second semiconductor chip 320) to the first and second semiconductor chips, and including first wiring lines (Fig.2-8 and [0084-0085]; a fourth wire 250, a fifth wire 240, and a sixth wire 260 extending between the first semiconductor chip 310 and first , second bonding regions BR1 and BR2) extending from the first semiconductor chip toward at least one of the first and second side surfaces and second wiring lines (Fig.2-8 and [0084-0085]; a first wire 150, a second wire 140, a third wire 160 extending between the second semiconductor chip 320 and first, second bonding regions BR1 and BR2) extending from the second semiconductor chip toward at least one of the first and second side surfaces, a backside wiring (Fig.8 and [0084-0085]; wiring layout view illustrating a second surface 110b of a film substrate 110) positioned between the rear protective layer and the rear surface of the film substrate, electrically connected (Fig.2-8 and [0089]; at least part of the first wire 150 may extend along the second surface 110b of the film substrate 110) to at least one of the first and second semiconductor chips, and including third wiring lines extending (Fig.8 and [0084-0085]; first wire 150 and second wire 250 extend along the second surface 110b between the first and second semiconductor chip 310, 320 and second bonding region BR2) from one of the first and second semiconductor chips toward at least one of the first and second side surfaces, input terminals adjacent to each other to be arranged along the second direction and exposed (attached Fig. 7 below and Fig.2,7 and [0056, 0098]; the first and second bonding pads 144 and 244 formed on the first surface 110a of the first bonding region BR1 and the first and second bonding pads 144 and 244 exposed by a resist film 120 along the X-direction) from the front protective layer on an end of the front wiring adjacent to the first side surface, and output terminals adjacent to each other to be arranged along the second direction and exposed (attached Fig. 7 below and Fig.2,7 and ¶ 0058, 0100; the third, fourth, fifth, and sixth bonding pads 154, 164, 254, and 264 formed on the first surface 110a of the second bonding region BR2 and exposed by a resist film 120 along the X-direction) from the front protective layer on an end of the front wiring adjacent to the second side surface.
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Min substantially discloses the invention including a first semiconductor chip and a second semiconductor chip disposed on the front surface of the film substrate and spaced apart in the second direction but silent about each extending lengthwise in the first direction to have short sides extending in the second direction and long sides extending in the first direction. However, Naitoh teaches that each chip extending lengthwise in the first direction to have short sides extending in the second direction and long sides extending in the first direction (attached Fig. 3 below).
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It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Min by providing each chip extending lengthwise in the first direction to have short sides extending in the second direction and long sides extending in the first direction, so that mounting a semiconductor chip on a flexible substrate obtained from a tape carrier arranged as above enables downscaling of the flexible substrate and efficient use of the tape carrier, contributing to high yields [0040].
Regarding claim 9, Min discloses; the front wiring and the backside wiring are electrically connected to each other through vias penetrating through the film substrate (Fig.9 and ¶ 0091; the first via 150v1 penetrate the film substrate 110. The first via 150v1 connect the first extended portion 150a and the second extended portion 150b).
Regarding claim 10, Min discloses; the plurality of wiring patterns further include a bypass pattern directly connecting at least some of the input terminals and at least some of the output terminals (Fig.2,7 and ¶ 0065; the direct wires 330 connect the first and second bonding regions BR1 and BR2).
Regarding claim 11, Min discloses; the first and second semiconductor chips include a source driving chip and a gate driving chip, respectively (Fig.2-7 and ¶ 0034; the semiconductor packages 100 electrically connected to the display panel 500 and perform the functions of a gate driver or a source driver).
Regarding claim 12, Min discloses; the front wiring and the backside wiring include at least one of a source input pattern connecting the first semiconductor chip to the input terminals, a source output pattern connecting the first semiconductor chip to the output terminals, a gate input pattern connecting the second semiconductor chip to the input terminals, and a gate output pattern connecting the second semiconductor chip to the output terminals (Fig.2-8 and ¶ 0030,0034; the driver printed circuit 400 connected to first sides of the semiconductor packages 100 and the semiconductor packages 100 may be electrically connected to the display panel 500 and may perform the functions of a gate driver or a source driver).
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Min, US 2020/0211972, in view of Naitoh, US 2006/0060949 as applied to claims 1and 9-12 above, and further in view of Aota- WO 2014034102.
Regarding claims 2-3, Min in view Naitoh substantially discloses the invention including; the first and second bonding pads 144 and 244 formed on the first bonding region BR1 and the third, fourth, fifth, and sixth bonding pads 154, 164, 254, and 264 formed on the second bonding region BR2 but is silent about a distance between the output terminals adjacent to each other is greater than a distance between the input terminals adjacent to each other in claim 2 and the distance between the input terminals is in a range from about 5 µm to about 25 µm, and the distance between the output terminals is in a range from about 30 µm to about 60 µm in claim 3. However, Aota shows that the arrangement pitch of adjacent input connection terminals 21 in the plurality of input connection terminals 21 is, for example, about 14 μm to 16 μm on average and the arrangement pitch of adjacent output connection terminals 25 in the plurality of output connection terminals 25 is, for example, about 60 μm to 120 μm on average (Fig.3 and Page 5; ¶ 7, Page 6; ¶ 1). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Min in view Naitoh by providing a distance between the output terminals adjacent to each other is greater than a distance between the input terminals adjacent to each other in claim 2 and the distance between the input terminals is in a range from about 5 µm to about 25 µm, and the distance between the output terminals is in a range from about 30 µm to about 60 µm in claim 3, to provides a good conduction state between the IC chip and the liquid crystal display panel with a configuration capable of supporting ultra-high density mounting. (Page 12; ¶ 4).
Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Min, US 2020/0211972, in view of Naitoh, US 2006/0060949 as applied to claims 1 and 9-12 above, and further in view of Jung- US 2022/0246530.
Regarding claims 4-5, Min discloses; each of the first side surface and the second side surface has a first length (Fig.2-8; film substrate 110 has opposite side surfaces, opposing each other in Y-direction, extending length in X-direction), and each of the third side surface and the fourth side surface has a second length (Fig.2-8; film substrate 110 has opposite side surfaces, opposing each other in X-direction, extending length in Y-direction). Min in view Naitoh substantially discloses the invention including film substrate has opposite side surfaces, extending in X-direction with first length and opposite side surfaces, extending in Y-direction with second length but silent about the first length is greater than the second length in claim 4 and the first length is in a range from about 180 mm to about 220 mm, and the second length is in a range from about 30 mm to about 70 mm in claim 5. However, Jung shows that a length 210L in X-direction is greater than the length 210S in Y-direction and a short axis length 210S of the bridge film 210, about 35 mm to about 156 mm (Fig. 4 and ¶ 0075). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Min in view Naitoh by providing the first length is greater than the second length in claim 4 and the first length is in a range from about 180 mm to about 220 mm, and the second length is in a range from about 30 mm to about 70 mm in claim 5, to provides a chip-on-film (COF) package capable of improving a dead space of a display panel, and a display apparatus including the COF package (¶ 0004).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Min, US 2020/0211972 in view of Naitoh, US 2006/0060949 as applied to claims 1 and 9-12 above, in view of Kang, US 8154120.
Regarding claim 13, Min discloses; the film substrate includes a first region in which the plurality of wiring patterns are disposed and which extends in the second direction (Fig.2-8 and ¶ 0084-0085; wiring layout view illustrating a first surface 110a of a film substrate 110 extends widthwise in X-direction), and a second region disposed on opposite sides of the first region adjacent to the first side surface and the second side surface (Fig.2-8 and ¶ 0084-0085; side regions adjacent to the first bonding region BR1 and the second bonding region BR2). Min in view of Naitoh substantially discloses the invention including the wiring patterns are disposed and which extends in the Y-direction but is silent about the second region has through-holes arranged in the second direction. However, Kang shows that sprocket holes 74 of a base film 72 are provided along a line in the horizontal direction X (Fig. 4 and Col. 5; Ln. 30-32).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Min in view of Naitoh by providing the first semiconductor chip and the second semiconductor chip are spaced apart in the second direction so that the effective TCP (or COF) has a horizontal width a width of the X direction equal to the horizontal width of the base film (Fig. 4 and Col. 5; Ln. 46-49).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 have been considered but are moot because the new ground of rejection has been applied.
102 and 103 rejections with new set of references, such as Naitoh, US 2006/0060949 and Min, US 2020/0211972, in view of Naitoh, US 2006/0060949 have been applied. Please see the rejections above.
Regarding applicant’s argument that Min and Chikawa fails to disclose input and output pads that are arranged in the same direction as a short side of the semiconductor chips. Rather, each COF (“chip on FPC (Flexible Printed Circuit)”) in Chikawa, similar to Min, depicts what appear to be leads for the COF arranged in the same direction as long sides of the associated semiconductor element. However new reference Naitoh discloses this orientation, please see the rejection above.
In response to applicant’s argument that Ayota does not disclose a film package, rather Ayota explicitly relates to a device for mounting semiconductor chip directly on a display panel, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Min only takes the teachings from Ayota.
Allowable Subject Matter
Claims 6, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights