DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II in the reply filed on December 10, 2025 is acknowledged.
Claims 18-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 10, 2025.
It is noted for clarity of the record that new claim 24 has changed independent claim 6 into a linking claim. Upon allowance of claim 6, claim 24 being dependent on claim 6, would be treated as a product-by-process claim. The language, term, or phrase “produced by a method comprising”, is directed towards the process of making a silicon carbide MOSFET device. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “produced by a method comprising” only requires a silicon carbide MOSEFT device.
Claim 6 link inventions Group II and a new method to produce Group II. The restriction requirement between the linked inventions is subject to the nonallowance of the linking claim, claim 6. Upon the indication of allowability of the linking claim, the restriction requirement as to the linked inventions shall be withdrawn and any claims depending from or otherwise requiring all the limitations of the allowable linking claim will be rejoined and fully examined for patentability in accordance with 37 CFR 1.104 Claims that require all the limitations of an allowable linking claim will be entered as a matter of right if the amendment is presented prior to final rejection or allowance, whichever is earlier. Amendments submitted after final rejection are governed by 37 CFR 1.116; amendments submitted after allowance are governed by 37 CFR 1.312.
Applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, the allowable linking claim, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Where a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Objections
Claim 14 is objected to because of the following informalities:
Line 2 uses the term “polysilicon.” Polysilicon can apply to many different parts in a semiconductor device structure and can present confusion. [0126] of the instant application discloses a “polysilicon material” within the trench. Applicant is asked to use the same term for consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation “the field oxide layer” in line 2 and “oxide portions” in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 17 appears to require dependency from claim 16, instead of claim 14. For purposes of examination, Examiner will interpret claim 17 as dependent on claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8-12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et. al. (US 20230026868 A1), hereinafter Ji.
Regarding claim 6, Ji teaches a silicon carbide MOSFET device (Fig 3A MOSFET 100, [0116]), comprising: a) a silicon carbide substrate (Fig 8 substrate 122, [0109]) of a first dopant type (n-type, [0109]); b) a first silicon carbide layer (Fig 8 drift region 124, [0111]) of the first dopant type (n-type, [0109]) on top of the silicon carbide substrate (Fig 8 substrate 122, [0109]); c) a plurality of trenches (Fig 8 trenches 321, [0138]) partially formed in the first silicon carbide layer (Fig 8 drift region 124, [0111]); each of the plurality of trenches (Fig 8 trenches 321, [0138]) covered at its exterior with a gate oxide (Fig 8 gate insulating fingers 332, [0138]); d) a second silicon carbide layer (Fig 8 layer containing shielding region 329, [0138]; See annotated figure) of a second dopant type (p-type, [0138]) embedded in the first silicon carbide layer (Fig 8 drift region 124, [0111]); the second silicon carbide layer (Fig 8 layer containing shielding region 329, [0138]; See annotated figure) comprising a plurality of second portions (Fig 8 portions containing shielding region 329 under the trench 321); e) a third silicon carbide layer (Fig 8 well region 126, [0112]; See annotated figure) of the second dopant type (p-type, [0112]) located above at least part of the second silicon carbide layer (Fig 8 layer containing shielding region 329, [0138]; See annotated figure); and f) a fourth silicon carbide layer (Fig 8 layer containing source region 128, [0112]; See annotated figure) located above at least part of the third silicon carbide layer Fig 8 well region 126, [0112]; See annotated figure; wherein, the gate oxide Fig 8 gate insulating fingers 332, [0138] of each of the plurality of trenches (Fig 8 trenches 321, [0138]) comprises a bottom surface (Fig 8 bottom of trench 321) and a side surface (Fig 8 side of trench 321); a corresponding one of the plurality of second portions (Fig 8 portions containing shielding region 329 under the trench 321) located directly underneath the bottom surface (Fig 8 bottom of trench 321) of the gate oxide (Fig 8 gate insulating fingers 332, [0138]) of each of the plurality of trenches (Fig 8 trenches 321, [0138]); wherein the silicon carbide MOSFET device (Fig 3A MOSFET 100, [0116]) further comprises a plurality of resistors (Fig 4F gate resistors 176, [0124]) that are formed monolithically with the silicon carbide substrate (Fig 8 substrate 122, [0109]) and the first (Fig 8 drift region 124, [0111]) to fourth silicon carbide layers (Fig 8 layer containing source region 128, [0112]; See annotated figure).
Examiner notes that Ji teaches a trench gate embodiment that can be implemented a similar manner as having planar gates ([0138]).
The language, term, or phrase “that are formed monolithically with the silicon carbide substrate and the first to fourth silicon carbide layers”, is directed towards the process of making a plurality of resistors with the silicon carbide substrate. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “that are formed monolithically with the silicon carbide substrate and the first to fourth silicon carbide layers” only requires a plurality of resistors with the first to fourth silicon carbide layers, which does not distinguish the invention from Ji, who teaches the structure as claimed.
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Regarding claim 8, Ji as modified in claim 6 teaches the corresponding one of the plurality of second portions (Fig 8 portions containing shielding region 329 under the trench 321) does not cover the (Fig 8) side surface (Fig 8 side of trench 321) of the gate oxide (Fig 8 gate insulating fingers 332, [0138]) of each of the plurality of trenches (Fig 8 trenches 321, [0138]).
Regarding claim 9, Ji as modified in claim 6 teaches the plurality of resistors (Fig 4F gate resistors 176, [0124]) is offset from (Figs 4A-4F are from Fig 3A gate pad region “A”, [0116]; the trenches are under the source bond pads 112-1 and 112-2) the plurality of trenches (Fig 8 trenches 321, [0138]) along a horizontal direction (Fig 3A).
Regarding claim 10, Ji as modified in claim 9 teaches the plurality of resistors (Fig 4F gate resistors 176, [0124]) is located above (Fig 4F gate resistors 176 are above semiconductor layer structure 120 containing the fourth silicon carbide layer of Fig 8) the fourth silicon carbide layer (Fig 8 layer containing source region 128, [0112]; See annotated figure of claim 6).
Regarding claim 11, Ji as modified in claim 6 teaches the plurality of resistors (Fig 4F gate resistors 176, [0124]) comprises a first resistor (Fig 5A left resistor from resistor circuit 190) and a second resistor (Fig 5A right resistor from resistor circuit 190); the first resistor (Fig 5A left resistor from resistor circuit 190) and the second resistor (Fig 5A right resistor from resistor circuit 190) both connected (electrically connected) to the plurality of second portions (Fig 8 portions containing shielding region 329 under the trench 321).
Regarding claim 12, Ji as modified in claim 11 teaches the first (Fig 5A left resistor from resistor circuit 190) and second resistors (Fig 5A right resistor from resistor circuit 190) constitute a voltage divider (resistor circuit 190 divides the voltage across the two resistors).
Regarding claim 14, Ji as modified in claim 6 teaches the plurality of resistors (Fig 4F gate resistors 176, [0124]) comprises a third resistor (Fig 5A left resistor from resistor circuit 180); the third resistor (Fig 5A left resistor from resistor circuit 180) connecting (electrically connecting; Fig 5A gate fingers 134 connect to bond pad 110) a polysilicon (gate fingers 134 comprise polysilicon, [0108]; the material of gate fingers 334 is not taught; however, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the same material as they perform the same function) in each of the plurality of the trenches (Fig 8 trenches 321, [0138]) to a gate electrode (Fig 3A gate bond pad 110, [0106]) of the silicon carbide MOSFET device (Fig 3A MOSFET 100, [0116]).
Regarding claim 15, Ji as modified in claim 14 teaches the gate electrode (Fig 3A gate bond pad 110, [0106]) is offset horizontally (Fig 3A) from a source electrode (Fig 3A source bond pads 112-1,112-2, [0106]) of the silicon carbide MOSFET device (Fig 3A MOSFET 100, [0116]).
Regarding claim 16, Ji as modified in claim 6 teaches a field oxide layer (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride) on top of the fourth silicon carbide layer (Fig 8 layer containing source region 128, [0112]; See annotated figure); the field oxide layer (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride) comprising a plurality of oxide portions (Fig 8 portion above trenches 321) each formed above and corresponding to one of the plurality of trenches (Fig 8 trenches 321, [0138]).
Regarding a field oxide layer formed above the trenches. Ji teaches the inter-metal dielectric pattern 150 may comprise one or more of a silicon oxide pattern and a silicon nitride pattern ([0114]). Further, Ji teaches the inter-metal dielectric pattern 150 is used to electrically insulate the gate fingers 134 (334 in the case of Fig 8) from the source metallization structure 160 ([0114]). In pursuing the multilayer pattern arrangement of Ji, there are only two locations for an oxide pattern: between the trench/nitride and between nitride/source metallization structure. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that having an oxide layer of a multilayer pattern directly contacting the trench material would provide the protection desired by Ji. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 17, Ji as modified in claim 16 teaches a dielectric layer (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride) substantially on top of the field oxide layer (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride); the dielectric layer (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride) comprising a plurality of dielectric insulating portions (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride) each formed above and corresponding to one of the oxide portions (Fig 8 inter-metal dielectric pattern 150, [0114]; inter-metal dielectric pattern 150 may comprise one or more of an oxide and a nitride).
Regarding a dielectric layer formed above the oxide portions. Ji teaches the inter-metal dielectric pattern 150 may comprise one or more of a silicon oxide pattern and a silicon nitride pattern ([0114]). Further, Ji teaches the inter-metal dielectric pattern 150 is used to electrically insulate the gate fingers 134 (334 in the case of Fig 8) from the source metallization structure 160 ([0114]). In pursuing the multilayer pattern arrangement of Ji, there are only two locations for a dielectric layer: between the trench/oxide and between oxide/source metallization structure. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that having a nitride layer of a multilayer pattern directly contacting the oxide portion would provide the protection desired by Ji. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ji et. al. (US 20230026868 A1), hereinafter Ji, in view of Kim et. al. (US 20250072044 A1), hereinafter Kim, with supporting evidence by Kumagai (US 20190081170 A1).
Ji as modified in claim 6 teaches the first dopant type (n-type, [0109]) is N and the second dopant type (p-type, [0138]) is P; the second (Fig 8 layer containing shielding region 329, [0138]; See annotated figure of claim 6) and third silicon carbide layers (Fig 8 well region 126, [0112]; See annotated figure of claim 6) being P- layers (p-type, [0138]); the fourth silicon carbide layer (Fig 8 layer containing source region 128, [0112]; See annotated figure of claim 6) comprising N+ regions ([0112]).
Ji fails to teach the fourth silicon carbide layer comprising P+ and N+ regions.
Regarding the fourth silicon carbide layer comprising P+ and N+ regions. Ji teaches the fourth silicon carbide layer comprising P and N+ regions. Kim teaches fourth silicon carbide layer (Fig 2C layer containing source region 250 and upper portion 134, [0062] corresponds to Ji: Fig 8 layer containing source region 128, [0112]; See annotated figure of claim 6) comprising P+ (Fig 2C upper portion 134, [0061]) and N+ (Fig 2C source region 140, [0062] corresponds to Ji: [0079]) regions. As an example, Kumagai also teaches a silicon carbide layer comprising P+ (Fig 3 contact region 25, [0127]) and N+ (Fig 3 source region 24, [0127] corresponds to Ji: [0079]) regions. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the fourth silicon carbide layer can comprise P or P+ regions. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest art is Ji et. al. (US 20230026868 A1), hereinafter Ji.
Ji fails to teach the first resistor (Fig 5A left resistor from resistor circuit 190) is electrically connected to a source electrode of the silicon carbide MOSFET device (Fig 3A MOSFET 100, [0116]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mimura et. al. (US 20240290616 A1) teaches discrete two layers on a trench gate.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813