DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment is made of applicant’s amendment, filed on 16 April 2026. The changes and remarks disclosed therein have been considered.
Claims 1-20 are pending in the application. Claims 1, 8-9, 11 and 16 are currently amended. Claims 1, 11 and 16 are independent claims. Claims 1-10 are withdrawn from further consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishikawa et al. (US 9,691,781) (hereinafter, “Nishikawa”).
Re: independent claim 11, Nishikawa discloses in figs. 5 and 10-19 a three-dimensional (3D) NAND memory structure, comprising: first and second decks (including 1002, 1003 in the first deck and including 1602, 1603 in the second deck), each comprising a plurality of tiers of memory cells (fig. 5) and composed of conductive layers (1002, 1602) interposed between isolation layers (1003, 1603), each tier of memory cells comprising a two-dimensional (2D) array of floating gate memory cells (fig. 5, col 6 ll. 25-29) formed in a conductive layer (1002, 1602); a silicon nitride (SiN) layer (1050, col 14 ll. 36-37) disposed between a top isolation layer (1003) in the first deck and a bottom isolation layer (1603) in the second deck; and a plurality of vertical pillars (1902, 1903), passing through the memory cells in the conductive layers (1002, 1602) and isolation layers (1003, 1603) in the first and second decks and passing through the SiN layer (1050), wherein a diameter of a portion (1903) of a first vertical pillar passing through the SiN layer (1050) is greater than a diameter of a portion (1902) of the first vertical pillar passing through the bottom isolation layer (1603) in the second deck; wherein a wall of the first vertical pillar is discontinuous at an interface of the SiN layer and a top isolation layer of the first deck (1006 in fig. 10, see also fig. 18).
Re: claim 12, Nishikawa discloses in figs. 5 and 10-19 the 3D NAND memory structure of claim 11, wherein the diameter of the portion (including 1006) of a vertical pillar passing through the SiN layer (1050) is greater than a diameter of a portion (1005) of the vertical pillar passing through the top isolation layer (1003) in the first deck.
Re: claim 13, Nishikawa discloses in figs. 5 and 10-19 the 3D NAND memory structure of claim 11, wherein an oxide residual in an upper corner of a portion of a vertical pillar passing through the SiN layer is eliminated or substantially eliminated (This is a product-by-process limitation, see MPEP § 2113. Additionally, this is a negative limitation that does not require an oxide residual to be present.).
Re: claim 14, Nishikawa discloses in figs. 5 and 10-19 the 3D NAND memory structure of claim 11, wherein the vertical pillars (including 1902, 1903) have a profile from top to bottom comprising: a first portion (1902) passing through layers in the second deck (1602, 1603) having a slight amount of taper (col 9 ll. 16-18), wherein a diameter at a top isolation layer (1603) in the second deck is greater than a diameter in the bottom isolation layer (1603) of the second deck; a second portion (1006) passing through the SiN layer (1050); and a third portion (1903) passing through layers in the first deck having a slight amount of taper (col 9 ll. 16-18), wherein a diameter at the top isolation layer (1003) in the first deck is greater than a diameter in a bottom isolation layer of the first deck (1003).
Re: claim 15, Nishikawa discloses in figs. 5 and 10-19 the 3D NAND memory structure of claim 11, wherein the vertical pillars have an outer sidewall comprising tunnel dielectric film (664 in fig. 5) over which a channel conductor (665 in fig. 5) is formed.
Re: independent claim 16, Nishikawa discloses in figs. 1, 5 and 10-19 an apparatus, comprising: one or more three-dimensional (3D) NAND memory structures including; first and second decks (including 1002, 1003 in the first deck and including 1602, 1603 in the second deck), each comprising a plurality of tiers of memory cells (fig. 5) and composed of conductive layers (1002, 1602) interposed between isolation layers (1003, 1603), each tier of memory cells comprising a two-dimensional (2D) array of floating gate memory cells (fig. 5, col 6 ll. 25-29) formed in a conductive layer (1002, 1602); a silicon nitride (SiN) layer (1050) disposed between a top isolation layer (1003) in the first deck and a bottom isolation layer (1603) in the second deck; a plurality of vertical pillars (1902, 1903), passing through the memory cells in the conductive layers (1002, 1602) and isolation layers (1003, 1603) in the first and second decks and passing through the SiN layer (1050), wherein a diameter of a portion (1903) of a first vertical pillar passing through the SiN layer (1050) is greater than a diameter of a portion (1902) of the first vertical pillar passing through the bottom isolation layer (1603) in the second deck, wherein a wall of the first vertical pillar is discontinuous at an interface of the SiN layer and a top isolation layer of the first deck (1006 in fig. 10, see also fig. 18); a controller (122), operative coupled to each of the one or more 3D NAND memory devices structures (126); and a host interface (140).
Re: claim 17, Nishikawa discloses in figs. 1, 5 and 10-19 the apparatus of claim 16, where the one or more memory structures comprise 3D NAND dies (fig. 5).
Re: claim 18, see claim 13 rejection above.
Re: claim 19, see claim 14 rejection above.
Re: claim 20, Nishikawa discloses in figs. 1, 5 and 10-19 the apparatus of claim 16, wherein the apparatus comprises a solid-state drive (SSD) (col 5 ll. 58-64).
Response to Arguments
Applicant’s arguments with respect to claims 11-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 4/29/2026
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