DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 1-10 are withdrawn from further consideration.
Election/Restrictions
Applicant’s election without traverse of Group II: Claims 11-20 in the reply filed on 29 December 2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2021/0066346) (hereinafter, “Lim”).
Re: independent claim 11, Lim discloses in figs. 3 and 9 a three-dimensional (3D) NAND memory structure comprising: first and second decks (GS1, GS2), each comprising a plurality of tiers of memory cells and composed of conductive layers (130) interposed between isolation layers (120), each tier of memory cells comprising a two-dimensional (2D) array of floating gate memory cells (including 143 in fig. 3) formed in a conductive layer (130); a silicon nitride (SiN) layer (interlayer insulating layer 125, [0033] discloses interlayer insulating layers may include SiN) disposed between a top isolation layer (uppermost layer of 120 in GS1) in the first deck (GS1) and a bottom isolation layer (lowermost layer 120 in GS2) in the second deck (GS2); and a plurality of vertical pillars (including 140), passing through the memory cells (including 143) in the conductive layers (130) and isolation layers (120) in the first and second decks (GS1, GS2) and passing through the SiN layer (125), wherein a diameter of a portion of a vertical pillar (including 140) passing through the SiN layer (125) is greater than a diameter of a portion of the vertical pillar (including 140) passing through the bottom isolation layer (lowermost layer 120 in GS2) in the second deck [0034].
Re: claim 12, Lim discloses in figs. 3 and 9 the 3D NAND memory structure of claim 11, wherein the diameter of the portion of a vertical pillar (including 140) passing through the SiN layer (125) is greater than a diameter of a portion of the vertical pillar (including 140) passing through the top isolation layer (uppermost layer 120 in GS1) in the first deck [0034].
Re: claim 13, Lim discloses in figs. 3 and 9 the 3D NAND memory structure of claim 11, wherein an oxide residual in an upper corner of a portion of a vertical pillar passing through the SiN layer is eliminated or substantially eliminated (This is a product-by-process limitation, see MPEP § 2113. Additionally, this is a negative limitation that does not require an oxide residual to be present.).
Re: claim 14, Lim discloses in figs. 3 and 9 the 3D NAND memory structure of claim 11, wherein the vertical pillars (including 140) have a profile from top to bottom comprising: a first portion passing through layers in the second deck (GS2) having a slight amount of taper [0034], wherein a diameter at a top isolation layer (uppermost layer 120 in GS2) in the second deck is greater than a diameter in the bottom isolation layer (lowermost layer 120 in GS2) of the second deck [0034]; a second portion passing through the SiN layer (125); and a third portion passing through layers in the first deck (GS1) having a slight amount of taper [0034], wherein a diameter at the top isolation layer (uppermost layer 120 in GS1) in the first deck is greater than a diameter in a bottom isolation layer (lowermost layer 120 in GS1) of the first deck.
Re: claim 15, Lim discloses in figs. 3 and 9 the 3D NAND memory structure of claim 11, wherein the vertical pillars have an outer sidewall comprising tunnel dielectric film (142) over which a channel conductor (140) is formed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2021/0066346) (hereinafter, “Lim”) in view of Hwang et al. (US 2012/0061744) (hereinafter, “Hwang”).
Re: independent claim 16, Lim discloses in figs. 3 and 9 an apparatus, comprising one or more three-dimensional (3D) NAND memory structures including, first and second decks (GS1, GS2), each comprising a plurality of tiers of memory cells and composed of conductive layers (130) interposed between isolation layers (120), each tier of memory cells comprising a two-dimensional (2D) array of floating gate memory cells (including 143 in fig. 3) formed in a conductive layer (130); a silicon nitride (SiN) layer (interlayer insulating layer 125, [0033] discloses interlayer insulating layers may include SiN) disposed between a top isolation layer (uppermost layer 120 in GS1) in the first deck (GS1) and a bottom isolation layer (lowermost layer 120 in GS2) in the second deck (GS2); a plurality of vertical pillars (including 140), passing through the memory cells (including 143) in the conductive layers (130) and isolation layers (120) in the first and second decks (GS1, GS2) and passing through the SiN layer (125), wherein a diameter of a portion of a vertical pillar (including 140) passing through the SiN layer (125) is greater than a diameter of a portion of the vertical pillar (including 140) passing through the bottom isolation layer (lowermost layer 120 in GS2) in the second deck [0034].
Lim does not disclose a controller, operative coupled to each of the 3D NAND memory devices; and a host interface.
Hwang discloses a controller, operative coupled to each 3D NAND memory device; and a host interface (figs. 14-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a controller and host interface in the apparatus for the purpose of controlling the memory device as exemplified by Hwang [0208].
Re: claim 17, Lim in view of Hwang discloses in figs. 3 and 9 of Lim the apparatus of claim 16, where the one or more memory structures comprise 3D NAND dies (fig. 1, [0207] of Lim).
Re: claim 18, see claim 13 rejection above.
Re: claim 19, see claim 14 rejection above.
Re: claim 20, Lim in view of Hwang discloses the apparatus of claim 16, wherein the apparatus comprises a solid-state drive (SSD) ([0215] of Hwang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishikawa et al. US 9,691,781 teach a vertical pillar having a diameter in a SiN layer greater than a diameter in a bottom isolation layer in a second deck.
Takekida US 10,763,276 teaches three dimensional memory including pillars having joint portions between columnar sections.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 1/13/2026