Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detail Action
On 08/23/2023, Application 18/237,089 is filed with claims 1-20;
That is a Non-Final Action.
Allowable Subject Matter
Claims 6-7, 13-14, and 19-20 are objected. They would be allowed if they were written in independent form.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach individually or in combination the FSM in the stall state to add a wait period and further advancing the FSM to the switch state.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 8-11, and 15-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea/ mental process without significantly more.
Claim 1:
(Prong 2A Analysis: Whether a Claim is Directed to a Judicial Exception)
Claim 1 recites the step of:
wherein the PMU is coupled to configure, a plurality of fields in a segment of a multi- segment datapath pipeline corresponding to an operation using a PMU context including a set of configuration bits to activate a segment of the multi-segment datapath pipeline, …
wherein the finite state machine (FSM) is configured to progress through a plurality of states corresponding to the plurality of PMU contexts, MPEP 2106.04(a);
This step can reasonably be performed in the human mind, through observation, judgement and opinion, with the aid of pen and paper, and therefore recite a mental process.
This judicial exception is not integrated into a practical application because the claim only recites mere instructions to apply an exception (a system), with additional elements comprising only insignificant extra-solution activity.
(2B Analysis: Whether a claim amounts to significantly more)
Claim 1 recites the additional element of:
a coarse-grained reconfigurable (CGR) processor including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs) configured to execute a dataflow graph;
which amount to additional elements that merely recite instruction to implement an abstract idea on a generate computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Claim 1 recites the additional element of:
a coarse-grained reconfigurable (CGR) processor including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs) configured to execute a dataflow graph,
a PCU coupled to a PMU via a multi-segment datapath pipeline,
the PCU coupled to receive a configuration file including PCU configuration data,
the PMU coupled to receive the configuration file including PMU configuration data, and a finite state machine (FSM),
wherein the PCU is coupled to configure a datapath including a plurality of functional units using the PCU configuration data for a plurality of to perform a task including a plurality of operations…
wherein the PMU is coupled to switch the plurality of fields in the segment using a plurality of PMU contexts, and….
wherein the FSM can switch from one state to another state to allow the PMU switch between any two contexts in the segment sequentially, and
wherein a plurality of FSMs corresponding to a plurality of segments can switch among a plurality states to allow switching of contexts in the plurality of segments concurrently; MPEP 2106.05(d);
amount to insignificant extra-solution activity of mere data outputting, and are additionally well-understood, routine or conventional activities for storing data. Further, these additional elements merely recite using computing components in their ordinary capacity to store data that is a result of the recited mental process, and thus can be considered mere instructions to apply an exception. These additional elements of insignificant extra-solution activity and mere instructions to apply are not indicative of integration into a practical application. Even when considered in combination, the additional elements do not provide an inventive concept, thus the claim is not eligible.
Claim 2:
(Prong 2A Analysis: Whether a Claim is Directed to a Judicial Exception)
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1.
The judicial exceptions recited in claims 2 and 1 are not integrated into a practical application because the recited additional elements comprise only mere instructions to apply an exception (The system) and insignificant extra-solution activity.
(2B Analysis: Whether a claim amounts to significantly more)
Claim 2 recites the additional element of:
wherein the operation can be a read or write operation; MPEP 2106.5(d);
amount to is merely an attempt to limit the use of the abstract idea to a particular technological environment and/or amount to insignificant extra-solution activity of mere data outputting, and are additionally well-understood, routine or conventional activities for storing data. Additionally, these additional elements merely recite using computing components in their ordinary capacity to store data that is a result of the recited mental process, and thus can be considered mere instructions to apply an exception. These additional elements of insignificant extra-solution activity and mere instructions to apply recited in claim 2 are not indicative of integration into a practical application. Even when considered in combination with the additional elements of claim 1, the additional elements do not provide an inventive concept, thus the claim is not eligible.
Claim 3:
(Prong 2A Analysis: Whether a Claim is Directed to a Judicial Exception)
Claim 3 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1.
The judicial exceptions recited in claims 3 and 1 are not integrated into a practical application because the recited additional elements comprise only mere instructions to apply an exception (The system) and insignificant extra-solution activity.
(2B Analysis: Whether a claim amounts to significantly more)
Claim 3 recites the additional element of:
wherein the plurality of states include an idle state, a drain state, a stall state, and a switch state; MPEP 2106.5(d);
amount to is merely an attempt to limit the use of the abstract idea to a particular technological environment and/or amount to insignificant extra-solution activity of mere data outputting, and are additionally well-understood, routine or conventional activities for storing data. Additionally, these additional elements merely recite using computing components in their ordinary capacity to store data that is a result of the recited mental process, and thus can be considered mere instructions to apply an exception. These additional elements of insignificant extra-solution activity and mere instructions to apply recited in claim 3 are not indicative of integration into a practical application. Even when considered in combination with the additional elements of claim 1, the additional elements do not provide an inventive concept, thus the claim is not eligible.
Claim 4:
(Prong 2A Analysis: Whether a Claim is Directed to a Judicial Exception)
Claim 4 is dependent on claims 1 and 3, and therefore inherits the same judicial exception recited in claims 1 and 3.
The judicial exceptions recited in claims 3 and 1 are not integrated into a practical application because the recited additional elements comprise only mere instructions to apply an exception (The system) and insignificant extra-solution activity.
(2B Analysis: Whether a claim amounts to significantly more)
Claim 4 recites the additional element of:
wherein in the idle state, the FSM is coupled to receive a PMU context switch request and further can progress to the drain state; MPEP 2106.5(d);
amount to is merely an attempt to limit the use of the abstract idea to a particular technological environment and/or amount to insignificant extra-solution activity of mere data outputting, and are additionally well-understood, routine or conventional activities for storing data. Additionally, these additional elements merely recite using computing components in their ordinary capacity to store data that is a result of the recited mental process, and thus can be considered mere instructions to apply an exception. These additional elements of insignificant extra-solution activity and mere instructions to apply recited in claim 4 are not indicative of integration into a practical application. Even when considered in combination with the additional elements of claims 1 and 3, the additional elements do not provide an inventive concept, thus the claim is not eligible.
Claims 8-11 are directed to method comprise the steps which the at least one process of platform of the system of claims 1-4 are configured to perform. Claims 8-11 recite the same limitations as claims 1-4, respectively; therefore, claims 8-11 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a method without significantly more for the same reasons presented with respect to claims 1-4. See above.
Claims 15-17 are directed to a non-transitory computer readable medium comprise the steps which the at least one process platform of the system of claims 1, and 3-4 are configured to perform. Claims 15-17 recite the same limitations as claims 1, and 3-4, respectively; therefore, claims 15-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a medium without significantly more for the same reasons presented with respect to claims 1 and 3-4. See above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran US Publicaton 2025/0123881 in view of Javadi US Publication 2020/0134308.
18/237,089
Sankaran US Publicaton 2025/0123881 in view of Javadi US Publication 2020/0134308
Claim 1
A data processing system comprising:
a coarse-grained reconfigurable (CGR) processor including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs) configured to execute a dataflow graph,
a PCU coupled to a PMU via a multi-segment datapath pipeline,
the PCU coupled to receive a configuration file including PCU configuration data,
the PMU coupled to receive the configuration file including PMU configuration data, and a finite state machine (FSM),
Sankaran teaches Graph Data Processing; p0874-0896; and configuring execution of the tasks through pipeline; (p1000-p1042)
Sankaran teaches an infinite state machine; p0167-p0353;
wherein the PCU is coupled to configure a datapath including a plurality of functional units using the PCU configuration data for a plurality of to perform a task including a plurality of operations,
wherein the PMU is coupled to configure, a plurality of fields in a segment of a multi- segment datapath pipeline corresponding to an operation using a PMU context including a set of configuration bits to activate a segment of the multi-segment datapath pipeline,
Sankaran configuring execution of the tasks through pipeline; (p1000-p1055)
Sankaran teaches segmenting code p0289-p0764;
Sankaran teaches time sliced fetching and decoding and simultaneous multithreading; (p1055-p1057)
Javadi teaches DFA that message-processing table records for the data plane circuit 110 and providing these records to the data plane circuit to program the data plane circuit to implement the state machine(s), and (3) the data plane circuit 110 using these records while processing the data messages to try to identify patterns in the characters stored in the data messages. Before translating the DFA into message-processing table records, the server 105 in some embodiments uses known graph partitioning techniques to simplify the DFA (e.g., by reducing the number of edges in the DFA). See Javadi p0030-p0040;
It would have been obvious at the time of the invention for a person ordinary skill in the art (POSITA) to include Javadi’s teaching with method of Sankaran in order to allow use to have dedicated circuitry to schedule task.
wherein the PMU is coupled to switch the plurality of fields in the segment using a plurality of PMU contexts, and
wherein the finite state machine (FSM) is configured to progress through a plurality of states corresponding to the plurality of PMU contexts,
wherein the FSM can switch from one state to another state to allow the PMU switch between any two contexts in the segment sequentially, and
wherein a plurality of FSMs corresponding to a plurality of segments can switch among a plurality states to allow switching of contexts in the plurality of segments concurrently.
Sankaran switching between task/data flow based on id and processing state (p0271-p0407)
Sankaran teaches finite state machine executed based on pattern recognized; (p897-p1333)
Javadi teaches ASIC that that includes multiple pipelines of message processing stages. These pipelines are organized into a set of ingress pipelines and a set of egress pipelines, with a traffic-managing crossbar switch in between these two sets to direct data message flows from ingress pipelines to egress pipelines (e.g., based on ingress-side message processing); (Javadi p0004-p0006)
It would have been obvious at the time of the invention for a person ordinary skill in the art (POSITA) to include Javadi’s teaching with method of Sankaran in order to allow use to have dedicated circuitry for pattern recognition.
Claim 2
The system of claim 1, wherein the operation can be a read or write operation.
Sankaran p0185;
Claim 3
The system of claim 1, wherein the plurality of states include an idle state, a drain state, a stall state, and a switch state.
Sankaran teaches drain command and state; p0624-p0628;
Claim 4
The system of claim 3, wherein in the idle state, the FSM is coupled to receive a PMU context switch request and further can progress to the drain state.
Sankaran teaches drain command and state; p0624-p0628;
Claim 5
The system of claim 4, wherein in the drain state, the FSM is coupled to allow the PMU to drain any current operations in the segment and then progress to the stall state.
Sankaran teaches stalled state; p0305-p0364;
As per claims 8-12, they are rejected under the same rationale as claims 1-5. See rejection above.
As per claims 15-18, they are rejected under the same rationale as claim 1 and 3-5. See rejection above.
Conclusion
Here is a list reference relates finite state machines:
Arsovski US Publication 2014/0201579: Method and Circuits for Disrupting Integrated Circuit Functions
Redfern US Publication 2018/0248562: Matrix compression Accelerator System and Method.
Musoll US Patent 12,061,793: Capacity-expanding Memory Control Component.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENG KE whose telephone number is (571)272-4062. The examiner can normally be reached M-F 6:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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PENG KE
Primary Examiner
Art Unit 2194
/PENG KE/Primary Examiner, Art Unit 2194