Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-6 and 15-20 without traverse in the reply filed on 12/22/2025 is acknowledged.
Claim Objections
Claim 15 is objected to because of the following informalities:
Applicant recites, “and heating the reservoir of conductive material effective to cause the reservoir of conductive material to volumetrically expand through the one or more openings to form one or more vias”. The Examiner believes that Applicant intended to recite, “and heating the reservoir of conductive material effectively to cause the reservoir of conductive material to volumetrically expand through the one or more openings to form one or more vias” in order for claim 15 to make grammatical sense. The Examiner is confident that the modified limitation is according to Applicant’s intent as the modified limitation is the same as a similar limitation in claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ishikawa et al US 20220336394 A1. Ishikawa et al will be referenced to as Ishikawa henceforth.
Regarding Claim 1,
Ishikawa teaches:
“A method of making a semiconductor device assembly (FIGs. 32A-H, annotated FIG. 32E #1), comprising:
providing a semiconductor die including:
first circuitry (annotated FIG. 32E #1);
second circuitry (annotated FIG. 32E #1) including a reservoir of conductive material (pad base portions 778B, [0360], annotated FIG. 32E #1: 778, and therefore 778B, may be copper.); and
an interlayer dielectric (first dielectric capping layer 987, [0362]) including one or more openings between the first circuitry and the reservoir of conductive material (encapsulated cavities 989, [0362], [0377]);
and heating the reservoir of conductive material effectively to cause the reservoir of conductive material to volumetrically expand through the one or more openings to form one or more vias in the one or more openings (pad base portion 778P, [0363] FIG. 32D-E: The copper of 778 is risen to an elevated temperature and fills the encapsulated cavities 989.) that electrically couple the first circuitry and the reservoir of conductive material (annotated FIG. 32E #1: There exists a conductive copper path between the first circuitry and the second circuitry.).”
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Annotated FIG. 32 E #1
Regarding Claim 2,
Ishikawa teaches:
“The method of claim 1, wherein:
the first circuitry comprises one or more traces (first memory-side metal level M1, [0166], FIG. 32E);
the second circuitry further comprises one or more contact pads configured to couple the semiconductor die and an additional semiconductor die (second metallic liner 778A, [0253]: 778A is part of pad base portion 778. This pad physically couples the semiconductor dies 700 and 900.);
and the one or more vias couple the one or more contact pads and the one or more traces (FIG. 32E: The vias are between and connected to the traces and the pads 778. Since the vias are conductive, the vias electrically couple the traces and the pads.).”
Regarding Claim 3,
Ishikawa teaches:
“The method of claim 1, wherein the first circuitry is above the second circuitry (FIG. 32E).”
Regarding Claim 4,
Ishikawa teaches:
“The method of claim 1, wherein the first circuitry comprises one or more through-silicon vias extending through the semiconductor die (through substrate via structures 388, [0159], [0364], annotated FIG. 32E #1: The substrate may be silicon. Silicon is a semiconductor.).”
Regarding Claim 5,
Ishikawa teaches:
“The method of claim 1, wherein:
the reservoir of conductive material comprises multiple discrete reservoirs of conductive material (annotated FIG. 32E #1);
and the one or more vias comprise a plurality of vias (annotated FIG. 32E #1), each of the plurality of vias separated by the interlayer dielectric and formed from a respective one of the multiple discrete reservoirs (annotated FIG. 32E #1).”
Regarding Claim 15,
Ishikawa teaches:
“A semiconductor die (FIGs. 32A-H, annotated FIG. 32E #1), wherein the semiconductor die is fabricated by: providing first circuitry at the semiconductor die (annotated FIG. 32E #1);
providing second circuitry (annotated FIG. 32E #1) including a reservoir of conductive material at the semiconductor die (pad base portions 778B, [0360], annotated FIG. 32E #1: 778, and therefore 778B, may be copper.);
providing an interlayer dielectric (first dielectric capping layer 987, [0362]) including one or more openings between the first circuitry and the reservoir of conductive material (encapsulated cavities 989, [0362], [0377]);
and heating the reservoir of conductive material effective to cause the reservoir of conductive material to volumetrically expand through the one or more openings to form one or more vias (pad base portion 778P, [0363] FIG. 32D-E: The copper of 778 is risen to an elevated temperature and fills the encapsulated cavities 989.) that electrically couple the first circuitry and the reservoir of conductive material (annotated FIG. 32E #1: There exists a conductive copper path between the first circuitry and the second circuitry.).”
Regarding Claim 16,
Ishikawa teaches:
“The semiconductor die claim 15, wherein:
the first circuitry comprises one or more traces (first memory-side metal level M1, [0166], FIG. 32E);
the second circuitry further comprises one or more contact pads configured to couple the semiconductor die and an additional semiconductor die (second metallic liner 778A, [0253]: 778A is part of pad base portion 778. This pad physically couples the semiconductor dies 700 and 900.);
and the one or more vias couple the one or more contact pads and the one or more traces (FIG. 32E: The vias are between and connected to the traces and the pads 778. Since the vias are conductive, the vias electrically couple the traces and the pads.).”
Regarding Claim 17,
Ishikawa teaches:
“The semiconductor die of claim 15, wherein the conductive material comprises copper ([0360], annotated FIG. 32E #1: 778, and therefore 778B, may be copper.).”
Regarding Claim 18,
Ishikawa teaches:
“The semiconductor die of claim 15, wherein:
the first circuitry comprises one or more traces (first memory-side metal level M1, [0166], FIG. 32E);
the second circuitry comprises one or more additional traces (second metal interconnect structures 780, [0361], FIG. 32E);
and the one or more vias couple the one or more traces and the one or more additional traces (FIG. 32E: The vias are between and connected to the traces and the additional traces 780. Since the vias are conductive, the vias electrically couple the traces and the pads.).”
Regarding Claim 19,
Ishikawa teaches:
“The semiconductor die of claim 15, wherein the first circuitry comprises one or more through-silicon vias extending through the semiconductor die (through substrate via structures 388, [0159], [0364], annotated FIG. 32E #1: The substrate may be silicon. Silicon is a semiconductor.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa as applied to claims 1-5 and 15-19 above.
Regarding Claim 6,
Ishikawa substantially teaches:
“The method of claim 1, wherein a volume of the reservoir of conductive material is at least 10 times a volume of the openings ([0363], FIG. 32E: 778P has a lesser area than 778B. 778P has a height of 10 nm to 50 nm. 778B has a height of greater than 100 nm. Therefore, one of ordinary skill in the art would find it reasonable to conclude that the volume of 778B may be at least 10 times the volume of 778P.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date that Ishikawa modifiable.
This is because Ishikawa does not explicitly teach the claimed range. However, Ishikawa teaches that the initial volume of a bonding pad directly affects the change of volume of the bonding pad (Ishikawa: [0287]: Notice the initial volume is the volume of 778B. The change in volume is the volume of 778P. This is because the change in volume is the final bond pad volume after expansion minus the initial bond pad volume prior to expansion.). The ratio of the initial volume to the change in volume is therefore a result effective variable. It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, this volume ratio to arrive at the claimed range. See MPEP 2144.05.II.B.
Regarding Claim 20,
Ishikawa teaches:
“The semiconductor die of claim 15, wherein a volume of the reservoir of conductive material is at least 10 times a volume of the openings ([0363], FIG. 32E: 778P has a lesser area than 778B. 778P has a height of 10 nm to 50 nm. 778B has a height of greater than 100 nm. Therefore, one of ordinary skill in the art would find it reasonable to conclude that the volume of 778B may be at least 10 times the volume of 778P.). ”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812