Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant’s amendment to the claims have overcome the claim objection. The claim objection is withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by a first interpretation of Ishikawa et al US 20220336394 A1. A first interpretation of Ishikawa et al will be referenced to as Ishikawa henceforth.
Regarding Claim 1,
Ishikawa teaches:
“A method of making a semiconductor device assembly (FIGs. 32A-H, annotated FIG. 32E #1- #3), comprising:
providing a semiconductor die (first semiconductor die 900, second semiconductor die 700, first dielectric capping layer 987, FIGs. 32A-H: These elements together create a larger semiconductor die.) including:
a semiconductor substrate (substrate 708, [0300], FIG. 32E), and a metallization layer formed over the semiconductor substrate (annotated FIG. 32 E #2: The metallization layer is a metallization layer because it contains interconnects. A layer may have many sublayers.), the metallization layer including:
first circuitry (annotated FIG. 32E #1)[[;]],
second circuitry (annotated FIG. 32E #1) opposite the first circuitry from the semiconductor substrate (annotated FIG. 32E #3),
the second circuitry (annotated FIG. 32E #1) including a reservoir of conductive material (pad base portions 778B, first metallic bonding structure 981, [0360], [363], [0367] annotated FIG. 32E #1: 778, and therefore 778B, may be copper. 981 is also made of copper. Since 778B is part of the second circuitry, and 981 is directly connected to 778, the reservoir is included in the second circuitry.); and
an interlayer dielectric (first dielectric capping layer 987, [0362]) including one or more openings between the first circuitry and the reservoir of conductive material (encapsulated cavities 989, [0362], [0377]);
a dielectric layer (optional dielectric spacer layer 910, [0164], FIG. 32E) having a bonding surface facing away from the semiconductor substrate, the bonding surface being an outermost surface of the semiconductor die (annotated FIG. 32 E #3: 910 is the furthest dielectric layer from a bottom side of 708. Therefore, the upper surface of 910 is an outermost surface of the semiconductor die.); and
heating the reservoir of conductive material effectively to cause the reservoir of conductive material to volumetrically expand through the one or more openings away from the bonding surface toward the semiconductor substrate ([0363], FIG. 32E: 981 may also be made of copper and may be heated to connect the dies 700 and 900 by expanding into the cavities 989. Because 989 is below 981, 981 must expand downwards. Therefore 981 expands away from 910 and toward 708.) to form one or more vias in the one or more openings (pad base portion 778P, [0363], FIG. 32D-E: The copper of 778 and 981 is risen to an elevated temperature and fills the encapsulated cavities 989.) that electrically couple the first circuitry and the reservoir of conductive material (annotated FIG. 32E #1: There exists a conductive copper path between the first circuitry and the second circuitry.).”
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Regarding Claim 4,
Ishikawa teaches:
“The method of claim 1, wherein the first circuitry comprises one or more through-silicon vias extending through the semiconductor die (through substrate via structures 388, [0159], [0364], annotated FIG. 32E #1: The substrate may be silicon. Silicon is a semiconductor.).”
Regarding Claim 5,
Ishikawa teaches:
“The method of claim 1, wherein:
the reservoir of conductive material comprises multiple discrete reservoirs of conductive material (annotated FIG. 32E #1);
and the one or more vias comprise a plurality of vias (annotated FIG. 32E #1), each of the plurality of vias separated by the interlayer dielectric and formed from a respective one of the multiple discrete reservoirs (annotated FIG. 32E #1).”
Claims 15, 17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by a second interpretation of Ishikawa et al US 20220336394 A1. A second interpretation of Ishikawa et al will be referenced to as Ishikawa #2 henceforth.
Regarding Claim 15,
Ishikawa #2 teaches:
“A semiconductor die (first semiconductor die 900, second semiconductor die 700, first dielectric capping layer 987, FIGs. 32A-H: These elements together create a larger semiconductor die.), wherein the semiconductor die is fabricated by:
providing a semiconductor substrate (substrate 908, [0159], FIG. 32E);
providing first circuitry adjacent to the at the semiconductor [[die]] substrate (annotated FIG. 32E #1);
providing second circuitry (annotated FIG. 32E #1) opposite the first circuitry from the semiconductor substrate, the second circuitry (annotated FIG. 32E #3) including a reservoir of conductive material (pad base portions 778B, first metallic bonding structure 981, [0360], [363], [0367] annotated FIG. 32E #1: 778, and therefore 778B, may be copper. 981 is also made of copper. Since 778B is part of the second circuitry, and 981 is directly connected to 778, the reservoir is included in the second circuitry.);
providing an interlayer dielectric (first dielectric capping layer 987, [0362]) including one or more openings between the first circuitry and the reservoir of conductive material (encapsulated cavities 989, [0362], [0377]);
providing a dielectric layer having a bonding surface facing away from the semiconductor substrate (second interconnect-level dielectric material layers 760, [0248], annotated FIG. 32E #4), the bonding surface being an outermost surface of the semiconductor die (annotated FIG. 32 E #4: 760 is the furthest dielectric layer from a top side of 908. Therefore, the lower surface of 760 is an outermost surface of the semiconductor die.);
and heating the reservoir of conductive material effectively to cause the reservoir of conductive material to volumetrically expand through the one or more openings away from the bonding surface toward the semiconductor substrate (pad base portion 778P, [0363] FIG. 32D-E: The copper of 778 is risen to an elevated temperature and fills the encapsulated cavities 989. 778 expands towards 908 and away from a bottom side of 760.) to form one or more vias (pad base portion 778P, [0363] FIG. 32D-E: The copper of 778 is risen to an elevated temperature and fills the encapsulated cavities 989.) that electrically couple the first circuitry and the reservoir of conductive material (annotated FIG. 32E #1: There exists a conductive copper path between the first circuitry and the second circuitry.).”
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Regarding Claim 17,
Ishikawa #2 teaches:
“The semiconductor die of claim 15, wherein the conductive material comprises copper ([0360], annotated FIG. 32E #1: 778, and therefore 778B, may be copper.).”
Regarding Claim 18,
Ishikawa #2 teaches:
“The semiconductor die of claim 15, wherein:
the first circuitry comprises one or more traces (first memory-side metal level M1, [0166], FIG. 32E);
the second circuitry comprises one or more additional traces (second metal interconnect structures 780, [0361], FIG. 32E);
and the one or more vias couple the one or more traces and the one or more additional traces (FIG. 32E: The vias are between and connected to the traces and the additional traces 780. Since the vias are conductive, the vias electrically couple the traces and the pads.).”
Regarding Claim 19,
Ishikawa #2 teaches:
“The semiconductor die of claim 15, wherein the first circuitry comprises one or more through-silicon vias extending through the semiconductor die (through substrate via structures 388, [0159], [0364], annotated FIG. 32E #1: The substrate may be silicon. Silicon is a semiconductor.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa as applied to claims 1 and 4-5.
Regarding Claim 6,
Ishikawa substantially teaches:
“The method of claim 1, wherein a volume of the reservoir of conductive material is at least 10 times a volume of the openings ([0363], FIG. 32E: 778P has a lesser area than 778B. 778P has a height of 10 nm to 50 nm. 778B has a height of greater than 100 nm. Therefore, one of ordinary skill in the art would find it reasonable to conclude that the volume of 778B may be at least 10 times the volume of 778P.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date that Ishikawa modifiable.
This is because Ishikawa does not explicitly teach the claimed range. However, Ishikawa teaches that the initial volume of a bonding pad directly affects the change of volume of the bonding pad (Ishikawa: [0287]: Notice the initial volume is the volume of 778B. The change in volume is the volume of 778P. This is because the change in volume is the final bond pad volume after expansion minus the initial bond pad volume prior to expansion.). The ratio of the initial volume to the change in volume is therefore a result effective variable. It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, this volume ratio to arrive at the claimed range. See MPEP 2144.05.II.B.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa #2 as applied to claims 15, 17-19.
Regarding Claim 20,
Ishikawa teaches:
“The semiconductor die of claim 15, wherein a volume of the reservoir of conductive material is at least 10 times a volume of the openings ([0363], FIG. 32E: 778P has a lesser area than 778B. 778P has a height of 10 nm to 50 nm. 778B has a height of greater than 100 nm. Therefore, one of ordinary skill in the art would find it reasonable to conclude that the volume of 778B may be at least 10 times the volume of 778P.). ”
It would have been obvious to one with ordinary skill in the art before the effective filing
date that Ishikawa #2 modifiable.
This is because Ishikawa does not explicitly teach the claimed range. However, Ishikawa teaches that the initial volume of a bonding pad directly affects the change of volume of the bonding pad (Ishikawa: [0287]: Notice the initial volume is the volume of 778B. The change in volume is the volume of 778P. This is because the change in volume is the final bond pad volume after expansion minus the initial bond pad volume prior to expansion.). The ratio of the initial volume to the change in volume is therefore a result effective variable. It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, this volume ratio to arrive at the claimed range. See MPEP 2144.05.II.B.
Allowable Subject Matter
Claims 2 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2,
Ishikawa/Ishikawa #2 fails to explicitly teach :
“the second circuitry further comprises one or more contact pads configured to couple the semiconductor die and an additional semiconductor die” In view of the rest of the limitations of claim 1.
Ishikawa/Ishikawa #2 fails to explicitly teach the above limitation because it is not obvious to combine the invention of Ishikawa/Ishikawa #2 with other art which teaches the above limitation.
This is because Ishikawa/Ishikawa #2 teaches two semiconductor dies, 700 and 900, which are put together to form a larger die. The first circuitry is in die 900. The second circuitry is in die 700. Therefore, for the limitations of the independent claim to be met, the cited semiconductor die must be the larger die. Because the second circuitry does not extend to the ends of the larger die, it cannot be that the second circuitry comprises contact pads which are configured to couple the semiconductor die and an additional semiconductor die.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Ishikawa/Ishikawa #2 to reach all of the limitations of the claim.
Regarding Claim 16, this claims depend on claim 15 and objectionable for the same reasons.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(2) rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new interpretations of Ishikawa.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“wherein the dielectric layer is in direct contact with the reservoir of conductive material”
It would overcome the current rejections for claims 1 and 15. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights